HD64F3067RVF datasheet, PDF - EEWORLD Datasheet

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HD64F3067RVF: DescriptionMicrocontroller, 32-Bit, FLASH, 13MHz, CMOS, PQFP100, QFP-100; CategoryThe embedded processor and controller Microcontrollers and processors; File Size3MB，924 Pages; ManufacturerHitachi （Renesas ）; Websitehttp://www.renesas.com/eng/

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HD64F3067RVF Overview

Microcontroller, 32-Bit, FLASH, 13MHz, CMOS, PQFP100, QFP-100

HD64F3067RVF Parametric

Parameter Name	Attribute value
Maker	Hitachi （Renesas ）
Parts packaging code	QFP
package instruction	FQFP,
Contacts	100
Reach Compliance Code	unknown
Has ADC	YES
Address bus width	24
bit size	32
maximum clock frequency	13 MHz
DAC channel	YES
DMA channel	YES
External data bus width	16
JESD-30 code	S-PQFP-G100
length	14 mm
Number of I/O lines	79
Number of terminals	100
Maximum operating temperature	75 °C
Minimum operating temperature	-20 °C
PWM channel	YES
Package body material	PLASTIC/EPOXY
encapsulated code	FQFP
Package shape	SQUARE
Package form	FLATPACK, FINE PITCH
Certification status	Not Qualified
ROM programmability	FLASH
Maximum seat height	3.05 mm
speed	13 MHz
Maximum supply voltage	5.5 V
Minimum supply voltage	3 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL EXTENDED
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	14 mm
uPs/uCs/peripheral integrated circuit type	MICROCONTROLLER
Base Number Matches	1

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H8/3067 Series

H8/3067, H8/3066, H8/3065

H8/3067 F-ZTAT

H8/3067F, H8/3067FR

Hardware Manual

ADE-602-135B

Rev. 3.0

22/2/99

Hitachi, Ltd.

Cautions

1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s

patent, copyright, trademark, or other intellectual property rights for information contained in

this document. Hitachi bears no responsibility for problems that may arise with third party’s

rights, including intellectual property rights, in connection with use of the information

contained in this document.

2. Products and product specifications may be subject to change without notice. Confirm that you

have received the latest product standards or specifications before final design, purchase or

use.

3. Hitachi makes every attempt to ensure that its products are of high quality and reliability.

However, contact Hitachi’s sales office before using the product in an application that

demands especially high quality and reliability or where its failure or malfunction may directly

threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear

power, combustion control, transportation, traffic, safety equipment or medical equipment for

life support.

4. Design your application so that the product is used within the ranges guaranteed by Hitachi

particularly for maximum rating, operating supply voltage range, heat radiation characteristics,

installation conditions and other characteristics. Hitachi bears no responsibility for failure or

damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,

consider normally foreseeable failure rates or failure modes in semiconductor devices and

employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi

product does not cause bodily injury, fire or other consequential damage due to operation of

the Hitachi product.

5. This product is not designed to be radiation resistant.

6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document

without written approval from Hitachi.

7. Contact Hitachi’s sales office for any questions regarding this document or Hitachi

semiconductor products.

Contents

Section 1

1.1

1.2

1.3

Overview

...........................................................................................................

1.4

Overview............................................................................................................................

Block Diagram...................................................................................................................

Pin Description ..................................................................................................................

1.3.1 Pin Arrangement ..................................................................................................

1.3.2 Pin Functions........................................................................................................

1.3.3 Pin Assignments in Each Mode............................................................................

Notes on Flash Memory R Version Model........................................................................

1.4.1 Pin Arrangement ..................................................................................................

1.4.2 Product Type Names and Markings .....................................................................

1.4.3 Differences in Flash Memory R Version..............................................................

Section 2

2.1

CPU

..................................................................................................................... 21

2.2

2.3

2.4

2.5

2.6

2.7

2.8

Overview............................................................................................................................

2.1.1 Features ................................................................................................................

2.1.2 Differences from H8/300 CPU.............................................................................

CPU Operating Modes ......................................................................................................

Address Space....................................................................................................................

Register Configuration ......................................................................................................

2.4.1 Overview ..............................................................................................................

2.4.2 General Registers..................................................................................................

2.4.3 Control Registers..................................................................................................

2.4.4 Initial CPU Register Values .................................................................................

Data Formats......................................................................................................................

2.5.1 General Register Data Formats ............................................................................

2.5.2 Memory Data Formats..........................................................................................

Instruction Set....................................................................................................................

2.6.1 Instruction Set Overview......................................................................................

2.6.2 Instructions and Addressing Modes .....................................................................

2.6.3 Tables of Instructions Classified by Function......................................................

2.6.4 Basic Instruction Formats.....................................................................................

2.6.5 Notes on Use of Bit Manipulation Instructions....................................................

Addressing Modes and Effective Address Calculation .....................................................

2.7.1 Addressing Modes................................................................................................

2.7.2 Effective Address Calculation..............................................................................

Processing States ...............................................................................................................

2.8.1 Overview ..............................................................................................................

2.8.2 Program Execution State ......................................................................................

2.8.3 Exception-Handling State ....................................................................................

2.9

2.8.4 Exception-Handling Sequences............................................................................

2.8.5 Bus-Released State ...............................................................................................

2.8.6 Reset State ............................................................................................................

2.8.7 Power-Down State................................................................................................

Basic Operational Timing..................................................................................................

2.9.1 Overview ..............................................................................................................

2.9.2 On-Chip Memory Access Timing ........................................................................

2.9.3 On-Chip Supporting Module Access Timing.......................................................

2.9.4 Access to External Address Space .......................................................................

Section 3

3.1

MCU Operating Modes

................................................................................ 61

3.2

3.3

3.4

3.5

3.6

Overview............................................................................................................................ 61

3.1.1 Operating Mode Selection.................................................................................... 61

3.1.2 Register Configuration ......................................................................................... 62

Mode Control Register (MDCR) ....................................................................................... 63

System Control Register (SYSCR).................................................................................... 64

Operating Mode Descriptions............................................................................................ 66

3.4.1 Mode 1.................................................................................................................. 66

3.4.2 Mode 2.................................................................................................................. 66

3.4.3 Mode 3.................................................................................................................. 66

3.4.4 Mode 4.................................................................................................................. 67

3.4.5 Mode 5.................................................................................................................. 67

3.4.6 Mode 6.................................................................................................................. 67

3.4.7 Mode 7.................................................................................................................. 67

Pin Functions in Each Operating Mode............................................................................. 68

Memory Map in Each Operating Mode............................................................................. 68

3.6.1 Note on Reserved Areas ....................................................................................... 68

Section 4

4.1

Exception Handling

........................................................................................ 75

4.2

4.3

4.4

4.5

4.6

Overview............................................................................................................................

4.1.1 Exception Handling Types and Priority ...............................................................

4.1.2 Exception Handling Operation .............................................................................

4.1.3 Exception Vector Table........................................................................................

Reset ..................................................................................................................................

4.2.1 Overview ..............................................................................................................

4.2.2 Reset Sequence.....................................................................................................

4.2.3 Interrupts after Reset ............................................................................................

Interrupts............................................................................................................................

Trap Instruction .................................................................................................................

Stack Status after Exception Handling ..............................................................................

Notes on Stack Usage........................................................................................................

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