The AS7C25512NTD32A/36A family is a high performance CMOS 16-Mbit synchronous Static Random Access Memory (SRAM) organized as
524,288 words × 32 or 36 bits and incorporates a LATE LATE Write.
This variation of the 16Mb+ synchronous SRAM uses the No Turnaround Delay (NTD
™
) architecture, featuring an enhanced write operation
that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied
to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data
to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-
write operations.
NTD
™
devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow-
through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD
™
,
write and read operations can be used in any order without producing dead bus cycles.
Assert R/W low to perform write cycles. Byte write enable controls write access to specific bytes, or can be tied low for full 18 bit writes. Write
enable signals, along with the write address, are registered on a rising edge of the clock. Write data is applied to the device two clock cycles
later. Unlike some asynchronous SRAMs, output enable OE does not need to be toggled for write operations; it can be tied low for normal
operations. Outputs go to a high impedance state when the device is de-selected by any of the three chip enable inputs. In pipelined mode, a
two cycle deselect latency allows pending read or write operations to be completed.
Use the ADV (burst advance) input to perform burst read, write and deselect operations. When ADV is high, external addresses, chip select, R/W pins
are ignored, and internal address counters increment in the count sequence specified by the LBO control. Any device operations, including burst, can
be stalled using the CEN=1, the clock enable input.
The AS7C25512NTD32A/36A operates with a 2.5V ± 5% power supply for the device core (V
DD
). These devices are available in a 100-pin
TQFP package and 165 BGA Ball Grid Array package.
Capacitance
Parameter
Input capacitance
I/O capacitance
Symbol
C
IN
C
I/O
I/O pins
Signals
Address and control pins
Test conditions
V
in
= 0V
V
in
= V
out
= 0V
Max
5
7
Unit
pF
pF
Burst order
Interleaved burst order LBO = 1
A1 A0 A1 A0 A1 A0 A1 A0
Starting address
First increment
Second increment
Third increment
0 0
0 1
1 0
1 1
0 1
0 0
1 1
1 0
1 0
1 1
0 0
0 1
1 1
1 0
0 1
00
Starting Address
First increment
Second increment
Third increment
Linear burst order LBO = 0
A1 A0 A1 A0 A1 A0 A1 A0
0 0
0 1
1 0
1 1
0 1
1 0
1 1
0 0
1 0
1 1
0 0
0 1
1 1
0 0
0 1
1 0
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Signal descriptions
Signal
CLK
CEN
A, A0, A1
DQ[a,b,c,d]
CE0, CE1,
CE2
ADV/LD
R/W
BW[a,b,c,d]
OE
LBO
FT
TDO
TDI
TMS
TCK
ZZ
NC
I/O Properties Description
I
I
I
I/O
I
I
I
I
I
I
I
O
I
I
O
I
-
CLOCK
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
ASYNC
STATIC
STATIC
SYNC
SYNC
SYNC
SYNC
ASYNC
-
Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.
Clock enable. When de-asserted high, the clock input signal is masked.
Address. Sampled when all chip enables are active and ADV/LD is asserted.
Data. Driven as output when the chip is enabled and OE is active.
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted. Are
ignored when ADV/LD is high.
Advance or Load. When sampled high, the internal burst address counter will increment in
the order defined by the LBO input value. (refer to table on page 2) When low, a new
address is loaded.
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE
operation. Is ignored when ADV/LD is high.
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE
command and BURST WRITE.
Asynchronous output enable. I/O pins are not driven when OE is inactive.
Count mode. When driven high, count sequence follows Intel XOR convention. When
driven low, count sequence follows linear convention. This input should be static when the
device is in operation.
Flow-through mode.When low, enables single register flow-through mode. Connect to V
DD
if unused or for pipelined operation.
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA only)
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only)
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.
(BGA only)
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA only)
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.
No connects.
Absolute maximum ratings
Parameter
Power supply voltage relative to GND
Input voltage relative to GND (input pins)
Input voltage relative to GND (I/O pins)
Power dissipation
DC output current
Storage temperature (plastic)
Temperature under bias (junction)
Symbol
V
DD
, V
DDQ
V
IN
V
IN
P
D
I
OUT
T
stg
T
bias
Min
–0.3
–0.3
–0.3
–
–
–65
–65
Max
+3.6
V
DD
+ 0.3
V
DDQ
+ 0.3
1.8
50
+150
+150
Unit
V
V
V
W
mA
o
o
C
C
Stresses greater than those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress rating only, and functional operation of
the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions may affect reliability.
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Synchronous truth table
CE0
H
X
X
L
L
X
X
CE1
X
L
X
H
H
X
X
CE2
X
X
H
L
L
X
X
ADV/LD
L
L
L
L
L
H
X
R/W BW[a,b]
X
X
X
H
L
X
X
X
X
X
X
L
X
1
X
OE
X
X
X
X
X
X
X
CEN
L
L
L
L
L
L
H
Address source
NA
NA
NA
External
External
Burst counter
Stall
CLK
L to H
L to H
L to H
L to H
L to H
L to H
L to H
Operation
Deselect, high-Z
Deselect, high-Z
Deselect, high-Z
Begin read
Begin write
Burst
2
Inhibit the CLK
1 Should be low for burst write, unless specific bytes need to be inhibited
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