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CN5850-800BG1521-SCP

Description
Micro Peripheral IC
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size182KB,2 Pages
ManufacturerCavium Networks
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CN5850-800BG1521-SCP Overview

Micro Peripheral IC

CN5850-800BG1521-SCP Parametric

Parameter NameAttribute value
MakerCavium Networks
package instruction,
Reach Compliance Codeunknown
Base Number Matches1
Multi-Core MIPS64 Processors
R
OCTEON Plus CN58XX 4 to 16-Core MIPS64-Based SoCs
Product Brief
The OCTEON
®
Plus CN58XX family of Multi-core MIPS64 processors targets intelligent networking, control plane,
storage, and wireless applications in next-generation equipment from 2 Gbps to full-duplex 10 Gbps (20 Gbps) performance.
The family includes 10 di erent software-compatible parts, with four to sixteen cnMIPS64 cores on a single chip that integrate
next-generation networking I/Os along with the most advanced security and application hardware acceleration to deliver
a 2x – 3x performance, power and real-estate value proposition over alternatives.
®
OVERVIEW
FEATURES
Pin and software compatible with the leading
OCTEON CN38XX/CN36XX family
4-16 cnMIPS™ CPU cores (MIPS64/32 compatible) with MMU
Available in 500 MHz to 800 MHz versions
Enhanced MIPS64 integer (Release2) instruction set
Dual-issue, ve-stage pipeline, optimized latencies
Auto instruction pre-fetching and advanced data
pre-fetching features to minimize memory stalls
BENEFITS
Market-leading performance
Up to 28.8 Billion instructions per second
Leading-edge application performance
-
Up to 30 Mpps 64B IP forwarding
-
Full-duplex up to 10 Gbps for TCP, IPsec, SSL, KASUMI
-
Up to 5 Gbps for Regular Expression
Compression/Decompression
High-performance coherent memory subsystem
Up to 2MB ECC protected 8-way set associative L2
cache with locking, partitioning features for optimal performance
Integrated mainstream 128/144-bit DDR2 memory controller with
ECC, up to DDR2-800
Optional, additional, low-latency 2x18-bit or 4x9-bit RLDRAM2
for content based processing, meta-data and TCAM connectivity
Packet I/O processing, QoS, TCP Acceleration
Support for IPsec, SSL, SRTP, WLAN and UMTS/LTE
security (includes DES, 3DES, AES-GCM, AES up to 256,
SHA1, SHA-2 up to SHA-512, RSA up to 8192, DH, KASUMI)
Regular Expression, Compression/Decompression
Up to 2 sets of I/Os - each con gurable as 4x
10/100/1000 Ethernet MACs (RGMII) or SPI-4.2
Integrated 64-bit, 133 MHz PCI-X host or slave
Double L1/L2 caches and up to 3x Interconnect
bandwidth along with 1 GHz Core delivers up to 2x
performance over OCTEON CN38XX
Sophisticated hardware based QoS support
Queuing, scheduling
Very low latency for real-time tra c
Integrated coprocessors for application acceleration
Reduced BOM cost with essential interfaces for
standalone Routers/Appliances, Line-card and
Services-card applications
Flexible architecture allows host and coprocessor
Implementations
Industry-standard programming model without any need
for Proprietary Tools or Micro-coding
Fully software compatible with OCTEON CN31XX and
CN30XX to deliver 1- 16 CPU scalability
2x – 3x advantage over alternative system architectures in
performance and power for L4-L7 data and security
services
2x performance/watt over OCTEON CN38XX
Integrated high-performance networking interfaces
Comprehensive development environment with Linux,
VxWorks, OSE and C/C++ support
Optimized power consumption: 15W – 40W
Package: 1521 FCBGA
OCTEON
®
Plus CN58XX
- Block Diagram
Optional 2x18-bit
RLDRAM2
SPI 4.2
or
4x RGMII
Packet
Interface
Secure
Vault
32x RegEx
Engines
Hyper Access Low Latency
Memory Controller
Packet
Packet
Boot/flash
GPIO
2xUART
Scheduler/
Sync. Order
Security
MIPS64 r2
Integer Core
32K Icache
Misc I/O
PCI-X
TCP Unit
I/O Bridge
Compress
/Decomp
64-bit,
133MHz
4 to 16
cnMIPS64
cores
Security
MIPS64 r2
Integer Core
32K Icache
16K Dcache
2K Write Buffer
Packet
Input
16K Dcache
2K Write Buffer
Coherent, Low Latency
Interconnect
2 MB
L2 Cache
2315 N. First Street
San Jose, CA 95131
T
408-943-7100
F
408-577-1992
E
sales@cavium.com
www.cavium.com
SPI 4.2
or
4x RGMII
Packet
Interface
I/O Bus
Packet
Output
Hyper Access
Memory Controller
DDR2 up to
800 MHz
72 or 144-bit wide

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