CD4027B datasheet, PDF - EEWORLD Datasheet

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CD4027B: DescriptionCD4027B CMOS Dual J-K Master-Slave Flip-Flop; Categorysemiconductor logic; File Size2MB，28 Pages; ManufacturerTexas Instruments; Websitehttp://www.ti.com.cn/; Environmental Compliance

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CD4027B Overview

CD4027B CMOS Dual J-K Master-Slave Flip-Flop

CD4027B Parametric

Parameter Name	Attribute value
VCC(Max)(V)	18
Voltage(Nom)(V)	10
Rating	Catalog
F @ nom voltage(Max)(Mhz)	8
VCC(Min)(V)	3
Approx. price(US$)	0.11 \| 1ku
tpd @ nom Voltage(Max)(ns)	130
Package Group	PDIP\|16,SOIC\|16,SO\|16,TSSOP\|16
ICC @ nom voltage(Max)(mA)	0.06
IOH(Max)(mA)	-1.5
IOL(Max)(mA)	1.5
Schmitt trigger	No
Bits(#)	2
Technology Family	CD4000

CD4027B Related Products

	CD4027B	CD4027BF	CD4027BF3A	JM38510/05152BEA	M38510/05152BEA	CD4027B-MIL
Description	CD4027B CMOS Dual J-K Master-Slave Flip-Flop	CMOS Dual J-K Master-Slave Flip-Flop 16-CDIP -55 to 125	CMOS Dual J-K Master-Slave Flip-Flop 16-CDIP -55 to 125	CMOS Dual J-K Master-Slave Flip-Flop 16-CDIP -55 to 125	CMOS Dual J-K Master-Slave Flip-Flop 16-CDIP -55 to 125	CD4027B-MIL CMOS Dual J-K Master-Slave Flip-Flop
Schmitt trigger	No	No	No	No	No	No
Brand Name	-	Texas Instruments	Texas Instruments	Texas Instruments	Texas Instruments	-
Parts packaging code	-	DIP	DIP	DIP	DIP	-
package instruction	-	DIP-16	DIP-16	DIP,	DIP-16	-
Contacts	-	16	16	16	16	-
Reach Compliance Code	-	not_compliant	not_compliant	not_compliant	not_compliant	-
series	-	4000/14000/40000	4000/14000/40000	4000/14000/40000	4000/14000/40000	-
JESD-30 code	-	R-GDIP-T16	R-GDIP-T16	R-GDIP-T16	R-GDIP-T16	-
length	-	19.305 mm	19.305 mm	19.56 mm	19.56 mm	-
Load capacitance (CL)	-	50 pF	50 pF	50 pF	50 pF	-
Logic integrated circuit type	-	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	J-K FLIP-FLOP	-
MaximumI(ol)	-	-0.0015 A	-0.0015 A	-0.0015 A	-0.0015 A	-
Number of digits	-	2	2	2	2	-
Number of functions	-	2	2	2	2	-
Number of terminals	-	16	16	16	16	-
Maximum operating temperature	-	125 °C	125 °C	125 °C	125 °C	-
Minimum operating temperature	-	-55 °C	-55 °C	-55 °C	-55 °C	-
Output polarity	-	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	COMPLEMENTARY	-
Package body material	-	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	-
encapsulated code	-	DIP	DIP	DIP	DIP	-
Package shape	-	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	-	IN-LINE	IN-LINE	IN-LINE	IN-LINE	-
method of packing	-	TUBE	TUBE	TUBE	TUBE	-
Peak Reflow Temperature (Celsius)	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
Maximum supply current (ICC)	-	0.6 mA	0.06 mA	0.06 mA	0.06 mA	-
Prop。Delay @ Nom-Sup	-	130 ns	130 ns	130 ns	130 ns	-
propagation delay (tpd)	-	300 ns	300 ns	300 ns	940 ns	-
Certification status	-	Not Qualified	Not Qualified	Not Qualified	Qualified	-
Maximum seat height	-	5.08 mm	5.08 mm	5.08 mm	5.08 mm	-
Maximum supply voltage (Vsup)	-	18 V	18 V	18 V	18 V	-
Minimum supply voltage (Vsup)	-	3 V	3 V	3 V	3 V	-
Nominal supply voltage (Vsup)	-	5 V	5 V	5 V	10 V	-
surface mount	-	NO	NO	NO	NO	-
technology	-	CMOS	CMOS	CMOS	CMOS	-
Temperature level	-	MILITARY	MILITARY	MILITARY	MILITARY	-
Terminal form	-	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	-
Terminal pitch	-	2.54 mm	2.54 mm	2.54 mm	2.54 mm	-
Terminal location	-	DUAL	DUAL	DUAL	DUAL	-
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
Trigger type	-	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	POSITIVE EDGE	-
width	-	7.62 mm	7.62 mm	6.92 mm	6.92 mm	-
minfmax	-	12 MHz	12 MHz	12 MHz	1 MHz	-
Base Number Matches	-	1	1	1	1	-

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