LH532100B-1
FEATURES
•
262,144 words
×
8 bit organization
•
Access time: 120 ns (MAX.)
•
Static operation
•
TTL compatible I/O
•
Three-state outputs
•
Single +5 V power supply
•
Power consumption:
Operating: 275 mW (MAX.)
Standby: 550
µW
(MAX.)
•
Mask-programmable control pin:
Pin 1 = OE
1
/OE
1
/DC
Pin 24 = OE/OE
•
Packages:
32-pin, 600-mil DIP
32-pin, 525-mil SOP
32-pin, 450-mil QFJ (PLCC)
32-pin, 8
×
20 mm
2
TSOP (Type I)
32-pin, 400-mil TSOP (Type II)
DESCRIPTION
The LH532100B-1 is a CMOS 2M-bit mask-program-
mable ROM organized as 262,144
×
8 bits. It is fabri-
cated using silicon-gate process technology.
D
7
CE
A
10
OE/OE
A
11
A
9
A
8
A
13
A
14
21
22
23
24
25
26
27
28
29
32-PIN DIP
32-PIN SOP
OE
1
/OE
1
/DC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
CMOS 2M (256K
×
8) MROM
PIN CONNECTIONS
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
DC
A
17
A
14
A
13
A
8
A
9
A
11
OE/OE
A
10
CE
D
7
D
6
D
5
D
4
D
3
532100B1-1
Figure 1. Pin Connections for DIP and
SOP Packages
GND
32-PIN QFJ
TOP VIEW
D
6
D
5
D
4
D
3
D
2
20 19 18 17 16 15 14
13
12
11
10
9
8
7
6
5
30 31 32
1
2
3
4
D
0
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CC
DC
A
16
A
15
OE
1
/OE
1
/DC
A
17
A
12
D
1
532100B1-7
Figure 2. Pin Connections for QFJ
(PLCC) Package
1
LH532100B-1
CMOS 2M MROM
32-PIN TSOP (Type I)
TOP VIEW
32-PIN TSOP (Type II)
TOP VIEW
A
11
A
9
A
8
A
13
A
14
A
17
DC
V
CC
OE
1
/OE
1
/DC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE/OE
A
10
CE
D
7
D
6
D
5
D
4
D
3
GND
D
2
D
1
D
0
A
0
A
1
A
2
A
3
532100B1-2
OE
1
/OE
1
/DC
A
16
A
15
A
12
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
D
0
D
1
D
2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
V
CC
DC
A
17
A
14
A
13
A
8
A
9
A
11
OE/OE
A
10
CE
D
7
D
6
D
5
D
4
D
3
NOTE:
Reverse bend available on request.
532100B1-3
Figure 3. Pin Connections for TSOP
(Type I) Package
Figure 4. Pin Connections for TSOP
(Type II) Package
2
CMOS 2M MROM
LH532100B-1
A
17
30
A
16
A
15
A
14
A
13
2
3
29
28
MEMORY
MATRIX
(262,144 x 8)
A
11
25
A
10
23
A
9
A
8
A
7
A
6
26
27
5
6
A
5
7
A
4
8
A
3
9
A
2
10
A
1
11
A
0
12
ADDRESS DECODER
ADDRESS BUFFER
A
12
4
COLUMN SELECTOR
SENSE AMPLIFIER
CE 22
CE
BUFFER
TIMING
GENERATOR
OUTPUT BUFFER
OE
1
/OE
1
/DC 1
OE/OE 24
OE
BUFFER
32
16
V
CC
GND
NOTE:
Pin numbers apply to the 32-pin DIP, SOP, QFJ, or TSOP (Type II).
13
D
0
14
D
1
15
D
2
17
D
3
18
D
4
19
D
5
20
D
6
21
D
7
532100B1-4
Figure 5. LH532100B-1 Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
NOTE
SIGNAL
PIN NAME
NOTE
A
0
– A
17
D
0
– D
7
CE
OE/OE
Address input
Data output
Chip enable input
Output enable input
1
OE
1
/OE
1
/DC
V
CC
GND
Output enable input
Power supply (+5 V)
Ground
1, 2
NOTES:
1. Active levels of OE/OE and OE
1
/OE
1
/DC are mask-programmable. Selecting DC allows the outputs to be active for both high and low levels
applied to this pin. It is recommended to apply either a HIGH or a LOW to the DC pin.
2. DC = Don’t care.
3
LH532100B-1
CMOS 2M MROM
TRUTH TABLE
CE
OE/OE
OE
1
/OE
1
DATA OUTPUT
SUPPLY CURRENT
H
L
L
L
X
L/H
X
H/L
X
X
L/H
H/L
High-Z
High-Z
High-Z
Output
Standby
Operating
Operating
Operating
NOTE:
X = H or L, High-Z = High-impedance
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
Supply voltage
Input voltage
Output voltage
Operating temperature
Storage temperature
V
CC
V
IN
V
OUT
Topr
Tstg
–0.3 to +7.0
–0.3 to V
CC
+ 0.3
–0.3 to V
CC
+ 0.3
0 to +70
–65 to +150
V
V
V
°C
°C
RECOMMENDED OPERATING CONDITIONS (T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
V
CC
4.5
5.0
5.5
V
DC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
MAX.
UNIT
NOTE
Input ‘High’ voltage
Input ‘Low’ voltage
Output ‘High’ voltage
Output ‘Low’ voltage
Input leakage current
Output leakage current
V
IH
V
IL
V
OH
V
OL
| I
Ll
|
| I
LO
|
I
CC1
I
OH
= – 400
µA
I
OL
= 2.0 mA
V
IN
= 0 V to V
CC
V
OUT
= 0 V to V
CC
t
RC
= 120 ns
t
RC
= 1
µs
t
RC
= 120 ns
t
RC
= 1
µs
CE = V
IH
CE = V
CC
– 0.2 V
f = 1 MHz
T
A
= 25°C
2.2
–0.3
2.4
V
CC
+ 0.3
0.8
V
V
V
0.4
10
10
50
45
45
40
3
100
10
10
V
µA
µA
mA
mA
mA
mA
mA
µA
pF
pF
1
2
2
3
3
Operating current
I
CC2
I
CC3
I
CC4
Standby current
Input capacitance
Output capacitance
I
SB1
I
SB2
C
IN
C
OUT
NOTES:
1. CE/OE/OE
1
= V
IH
, OE/OE
1
= V
IL
2. V
IN
= V
IH
or V
IL
, CE = V
IL
, outputs open
3. V
IN
= (V
CC
– 0.2 V) or 0.2 V, CE = 0.2 V, outputs open
4
CMOS 2M MROM
LH532100B-1
AC CHARACTERISTICS (V
CC
= 5 V
±10%,
T
A
= 0°C to +70°C)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable access time
Output enable delay time
Output hold time
CE to output in High-Z
OE to output in High-Z
t
RC
t
AA
t
ACE
t
OE
t
OH
t
CHZ
t
OHZ
120
120
120
50
10
50
ns
ns
ns
ns
ns
ns
1
NOTE:
1. This is the time required for the outputs to become high-impedance.
AC TEST CONDITIONS
PARAMETER
RATING
Input voltage amplitude
Input rise/fall time
Input reference level
Output reference level
Output load condition
0.6 V to 2.4 V
10 ns
1.5 V
0.8 V and 2.2 V
1 TTL + 100 pF
CAUTION
To stabilize the power supply, it is recommended that a high-frequency bypass capacitor be connected between
the V
CC
pin and the GND pin.
t
RC
A
0
- A
17
t
AA
(NOTE)
CE
t
ACE
(NOTE)
OE/OE
1
OE/OE
1
t
OE
(NOTE)
t
OHZ
t
OH
t
CHZ
D
0
- D
7
NOTE:
The output data becomes valid when the
last intervals, t
AA
, t
ACE
, or t
OE
, have concluded.
DATA VALID
532100B1-5
Figure 6. Timing Diagram
5
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