LH5116/H
FEATURES
•
2,048
×
8 bit organization
•
Access time: 100 ns (MAX.)
•
Power consumption:
Operating: 220 mW (MAX.)
Standby: 5.5
µW
(MAX.)
•
Single +5 V power supply
•
Fully-static operation
•
TTL compatible I/O
•
Three-state outputs
•
Wide temperature range available
LH5116H: -40 to +85°C
•
Packages:
24-pin, 600-mil DIP
24-pin, 300-mil SK-DIP
24-pin, 450-mil SOP
CMOS 16K (2K
×
8) Static RAM
DESCRIPTION
The LH5116/H are static RAMs organized as 2,048
×
8
bits. It is fabricated using silicon-gate CMOS process
technology. It features high speed access in read mode
using output enable (t
OE
).
PIN CONNECTIONS
24-PIN DIP
24-PIN SK-DIP
24-PIN SOP
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
1
I/O
2
I/O
3
GND
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
A
8
A
9
WE
OE
A
10
CE
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
5116-1
Figure 1. Pin Connections for DIP, SK-DIP,
and SOP Packages
1
LH5116/H
CMOS 16K (2K
×
8) Static RAM
ROW DECODERS
ROW ADDRESS
BUFFERS
A
0
8
A
5
3
A
6
2
A
7
1
A
8
23
A
9
22
A
10
19
I/O
1
9
I/O
2
10
I/O
3
11
I/O
4
13
I/O
5
14
I/O
6
15
I/O
7
16
I/O
8
17
MEMORY CELL
ARRAY
(128 x128)
24 V
CC
12 GND
CE
DATA CONTROL
COLUMN
I/O CIRCUIT
COLUMN DECODERS
COLUMN ADDRESS
BUFFERS
CE
CE 18
WE 21
OE 20
4
A
4
5
A
3
6
A
2
7
A
1
5116-2
Figure 2. LH5116/H Block Diagram
PIN DESCRIPTION
SIGNAL
PIN NAME
SIGNAL
PIN NAME
A
0
- A
10
CE
OE
WE
Address input
Chip Enable input
Output Enable input
Write Enable input
I/O
1
- I/O
8
V
CC
GND
Data input/output
Power supply
Ground
TRUTH TABLE
CE
OE
WE
MODE
I/O
1
- I/O
8
SUPPLY CURRENT
NOTE
L
L
H
L
NOTE:
1. X = H or L
X
L
X
H
L
H
X
X
Write
Read
Deselect
Outputs disable
D
IN
D
OUT
High-Z
High-Z
Operating (ICC)
Operating (I
CC
)
Standby (I
SB
)
Operating (I
CC
)
1
1
1
2
CMOS 16K (2K
×
8) Static RAM
LH5116/H
ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
RATING
UNIT
NOTE
Supply voltage
Input voltage
Operating temperature
Storage temperature
V
CC
V
IN
Topr
Tstg
-0.3 to +7.0
-0.3 to V
CC
+ 0.3
0 to +70
-40 to +85
-55 to +150
V
V
°C
°C
1
1
2
3
NOTES:
1. The maximum applicable voltage on any pin with respect to GND.
2. Applied to the LH5116/D/NA
3. Applied to the LH5116H/HD/HN
RECOMMENDED OPERATING CONDITIONS
1
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
Supply voltage
Input voltage
V
CC
V
IH
V
IL
4.5
2.2
-0.3
5.0
5.5
V
CC
+ 0.3
0.8
V
V
V
NOTE:
1. T
A
= 0 to 70°C (LH5116/D/NA), T
A
= -40 to +85°C (LH5116H/HD/HN)
DC CHARACTERISTICS
1
(V
CC
= 5 V
±10%)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Output ‘LOW’ voltage
Output ‘HIGH’ voltage
Input leakage current
Output leakage current
Operating current
Standby current
V
OL
V
OH
I
LI
I
LO
I
CC1
I
CC2
I
SB
I
OL
= 2.1 mA
I
OH
= -1.0 mA
V
IN
= 0 V to V
CC
CE = V
IH
, V
I/O
= 0 V to V
CC
Outputs open (OE = V
CC
)
Outputs open (OE = V
IH
)
CE
≥
V
CC
- 0.2 V
All other input pins = 0 V to V
CC
0.4
2.4
-1.0
-1.0
25
30
1.0
1.0
30
40
1.0
0.2
V
V
µA
µA
mA
mA
µA
2
3
4
NOTES:
1. T
A
= 0 to 70°C (LH5116/D/NA), T
A
= -40 to +85°C (LH5116H/HD/HN)
2. CE = 0 V; all other input pins = 0 V to V
CC
3. CE = V
IL
; all other input pins = V
IL
to V
IH
4. T
A
= 25°C
AC CHARACTERISTICS
1
(1) READ CYCLE (V
CC
= 5 V
±10%)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Read cycle time
Address access time
Chip enable access time
Chip enable Low to output in Low-Z
Output enable access time
Output enable Low to output in Low-Z
Chip disable to output in High-Z
Output disable to output in High-Z
Output hold time
t
RC
t
AA
t
ACE
t
CLZ
t
OE
t
OLZ
t
CHZ
t
OHZ
t
OH
100
100
100
10
40
10
0
0
10
40
40
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
2
2
NOTES:
1. T
A
= 0 to 70°C (LH5116/NA/D). T
A
= -40 to 85°C (LH5116H/HD/HN).
2. Active output to high-impedance and high-impedance to output active tests specified for a
±200
mV transition
from steady state levels into the test load.
3
LH5116/H
CMOS 16K (2K
×
8) Static RAM
(2) WRITE CYCLE
1
(V
CC
= 5 V
±10%)
PARAMETER
SYMBOL
MIN.
TYP.
MAX.
UNIT
NOTE
Write cycle time
Chip enable to end of write
Address valid time
Address setup time
Write pulse width
Write recovery time
Output active from end of write
WE Low to output in High-Z
Data valid to end of write
Data hold time
Output enable to output in High-Z
Output active from end of write
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
OW
t
WHZ
t
DW
t
DH
t
OHZ
t
OW
100
80
80
0
60
10
10
0
30
10
0
10
40
30
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
2
2
NOTES:
1. T
A
= 0 to +70°C (LH5116/D/NA), T
A
= -40 to +85°C (LH5116H/HD/HN)
2. Active output to high-impedance and high-impedance to output active tests specified for a
±200
mV transition
from steady state levels into the test load.
AC TEST CONDITIONS
PARAMETER
MODE
NOTE
Input voltage amplitude
Input rise/fall time
Timing reference level
Output load condition
NOTE:
1. Includes scope and jig capacitance.
0.8 V to 2.2 V
10 ns
1.5 V
1TTL + C
L
(100 pF)
1
DATA RETENTION CHARACTERISTICS
1
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
NOTE
Data retention voltage
Data retention current
Chip disable to data
retention
Recovery time
V
CCDR
I
CCDR
t
CDR
t
R
CE
≥
V
CCRC
- 0.2 V
CE
≥
V
CCDR
- 0.2 V,
V
CCDR
= 2.0 V
2.0
5.5
1.0
0.2
V
µA
ns
ns
3
2
0
t
RC
NOTES:
1. T
A
= 0 to +70°C (LH5116/D/NA), T
A
= -40 to +85°C (LH5116H/HD/HN)
2. T
A
= 25°C
3. t
RC
= Read cycle time
CAPACITANCE
1
(f = 1 MHz, T
A
= 25°C)
PARAMETER
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Input capacitance
Input/output capacitance
C
IN
C
I/O
V
IN
= 0 V
V
I/O
= 0 V
7
10
pF
pF
NOTE:
1. This parameter is sampled and not production tested.
4
CMOS 16K (2K
×
8) Static RAM
LH5116/H
t
CDR
V
CC
4.5 V
2.2 V
V
CCDR
CE
0V
DATA RETENTION MODE
t
R
CE
≥
V
CCDR
-0.2 V
5116-6
Figure 3. Low Voltage Data Retention
t
RC
A
0
- A
10
t
AA
t
ACE
CE
t
OE
OE
t
OLZ
t
CLZ
D
OUT
NOTE:
WE = "HIGH"
DATA VALID
t
OH
t
CHZ
t
OHZ
5116-3
Figure 4. Read Cycle
5
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