EEWORLDEEWORLDEEWORLD

Part Number

Search

LG1605DXB

Description
LG1605DXB Limiting Amplifier
Categoryaccessories   
File Size682KB,12 Pages
ManufacturerAgere System(LSI Logic)
Download Datasheet Compare View All

LG1605DXB Overview

LG1605DXB Limiting Amplifier

Data Sheet
February 1999
LG1605DXB Limiting Amplifier
Features
s
s
s
s
s
s
s
s
s
Digital video transmission
Interface between 1319 receiver and LG1600
clock and data regenerator
High-speed comparator
28 dB gain, 34 dB differential
Large dynamic range: >60 dB
Wideband response: 8 kHz to 3 GHz
Extremely low ±4 ps delay skew across input range
Complementary 50
I/Os
Surface-mount package
Standard ECL supply (400 mW)
s
Functional Description
The LG1605DXB is a GaAs wideband limiting ampli-
fier with differential inputs and outputs that provides
28 dB of gain (34 dB differential) and 3 GHz of band-
width in a 50
environment (Figure 1 shows the
block diagram). At low input levels, below 10 mV to
20 mV, the circuit behaves as a linear amplifier. At
higher levels, the device goes smoothly into limiting.
The device matches the performance of an AGC
amplifier but shows none of the AGC bouncing and
attack characteristics.
V
SS
7
GND
1, 4, 5, 6, 15, 16
Applications
s
Data/clock main amplifier SONET/SDH OC-48/
STM-16 transmission systems, DWDM systems
V
BR
8
110 pF
110 pF
V
–REF
V
–IN
V
+IN
V
+REF
110 pF
9
10
11
12
50
25 kΩ
+
50
+ –
– +
+ –
– +
25 kΩ
CHIP BOUNDARY
3
2
V
–OUT
V
+OUT
13
V
BF
14
V
BS
12-3214(F).r3
Figure 1. LG1605DXB Block Diagram

LG1605DXB Related Products

LG1605DXB TF1003C LG1605DXB-FLP
Description LG1605DXB Limiting Amplifier LG1605DXB Limiting Amplifier LG1605DXB Limiting Amplifier
DG9051/2/3: Low Voltage Monolithic CMOS Analog Switches and Multiplexers
DG9051/2/3: Low voltage monolithic CMOS analog switches and multiplexers, DG9051 is an 8-way multiplexer, DG9052 is a dual 4-way multiplexer, DG9053 is a 3-way single-pole double-throw (SPDT) switch, ...
frozenviolet Analog electronics
Essential FPGA comprehensive information for practical use
FPGA implementation of 800Mbps quasi-cyclic LDPC code encoderFPGA design and implementation of CCSDS satellite-borne image compression moduleResearch on speech recognition system based on FPGA and Nio...
V3FPGA2011 FPGA/CPLD
Based on the SPI protocol, using MSP430G2553 to control ADS1115, encountered difficulties
1. No Chinese information was found for ads1115. . . I don't know how to accurately set P1.2| Data In (UCA0SIMO) 2. I want to display the sampling results. Can the serial assistant be used? 3. I am ha...
songtaste Microcontroller MCU
How do I know what file in the /dev directory my driver is registered as in Linux? I'm a beginner and would like some advice.
How does Linux know what file the driver I wrote is registered as in the /dev directory, which part of the driver is implemented, and what macro declaration is used? I want to register my driver as a ...
回到当下 Linux and Android
Share STM32 485 bus communication test code
Additional note: One of the routines is implemented using the MODBUS protocol. In order to implement the MODBUS protocol, we transplanted a protocol stack called FREE MODBUS. Regarding the FREE MODBUS...
jiaxinhui2011 stm32/stm8
The same code, different running results in VC and EVC
The following code implements the function: when the mouse points to the button with ID IDC_BUTTON_TEST, a prompt message will appear, which is the ToolTip function. The code is very simple. The dialo...
daniel_zhang Embedded System

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 542  25  1989  489  895  11  1  41  10  19 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号