LF43891
DEVICES INCORPORATED
9 x 9-bit Digital Filter
LF43891
DEVICES INCORPORATED
9 x 9-bit Digital Filter
DESCRIPTION
The
LF43891
is a video-speed digital
filter that contains eight filter cells
(taps) cascaded internally and a shift-
and-add output stage. A 9 x 9 multi-
plier, three decimation registers, and a
26-bit accumulator are contained in
each filter cell. The output stage of the
LF43891 contains a 26-bit accumulator
which can add the contents of any
filter stage to the output stage accu-
mulator shifted right by 8 bits. 8-bit
unsigned or 9-bit two’s complement
format for data and coefficients can be
independently selected.
Expanded coefficients and word sizes
can be processed by cascading mul-
tiple LF43891s to implement larger
filter lengths without affecting the
sample rate. By reducing the sample
rate, a single LF43891 can process
larger filter lengths by using multiple
passes. The sampling rate can range
from 0 to 40 MHz. Over 1000 taps
may be processed without overflows
due to the architecture of the device.
The output sample rate can be re-
duced to one-half, one-third, or one-
fourth the input sample rate by using
the three decimation registers con-
tained in every filter cell. Matrix
multiplication, N x N spatial correla-
tions/convolutions, and other 2-D
operations for image processing can
also be achieved using these registers.
FEATURES
u
u
u
u
30 MHz Maximum Sampling Rate
320 MHz Multiply-Accumulate Rate
8 Filter Cells
8-bit Unsigned or 9-bit Two’s
Complement Data/Coefficients
u
26-bit Data Outputs
u
Shift-and-Add Output Stage for
Combining Filter Outputs
u
Expandable Data Size, Coefficient
Size, and Filter Length
u
User-Selectable 2:1, 3:1, or 4:1
Decimation
u
Replaces Harris HSP43891
u
84-pin PLCC, J-Lead
LF43891 B
LOCK
D
IAGRAM
DIN
8-0
9
DIENB, CIENB,
ERASE, DCM
1-0
5
CIN
8-0
9
FILTER
CELL 0
9
FILTER
CELL 1
9
FILTER
CELL 2
9
FILTER
CELL 3
9
FILTER
CELL 4
9
FILTER
CELL 5
9
FILTER
CELL 6
9
FILTER
CELL 7
9
COUT
8-0
ADR
2-0
3
26
26
26
26
26
26
26
26
COENB
MUX
26
SHADD
SENBL
SENBH
RESET
26
OUTPUT
STAGE
TO ALL CELLS
CLK
TO ALL REGISTERS
SUM
25-0
Video Imaging Products
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LF43891
DEVICES INCORPORATED
9 x 9-bit Digital Filter
F
IGURE
1. F
ILTER
C
ELL
D
IAGRAM
CIENB.D
DCM
0
.D
DCM
1
.D
LD
CIN
8-0
C REG
C
8-0
LD
D1 REG
1
MUX
LD
D2 REG
LD
D3 REG
1
MUX
TRI-STATE BUFFER
ON FILTER CELL 7 ONLY
COUT
8-0
COENB
0
D
8-0
0
C
8-0
DIENB.D
LD
DIN
8-0
X REG
X
8-0
M REG0
DCM
1
DCM
0
RESET
DIENB
CIENB
ADR
0
ADR
1
ADR
2
ERASE
LATCHES
DCM
1
.D
DCM
0
.D
RESET.D
DIENB.D
CIENB.D
ADR
0
.D
ADR
1
.D
ADR
2
.D
ERASE.D
RESET.D
ERASE.D
ACCUMULATOR
ACC
25-0
SIGN EXTENSION
25-18
17-0
M REG1
CELL n
CELL 0
CELL 1
CELL 2
CELL 3
CELL 4
CELL 5
CELL 6
CELL 7
ACC.D
25-0
ADR
0
ADR
1
ADR
2
DECODER
CELL n
D
Q
LD T REG
AOUT
25-0
CLK
RESET.D
TO ALL REGISTERS
TO ALL REGISTERS (EXCEPT ACCUMULATOR AND T-REGISTER)
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LF43891
DEVICES INCORPORATED
9 x 9-bit Digital Filter
F
IGURE
2.
O
UTPUT
S
TAGE
D
IAGRAM
SHADD
ADR
2-0
.D
26
26
26
26
26
26
26
26
FILTER CELL DESCRIPTION
9-bit coefficients are loaded into the
C register (CIN
8-0
) and are output as
COUT
8-0
(the COENB signal enables
the COUT
8-0
outputs). The path
taken by the coefficients varies
according to the decimation mode
chosen. With no decimation, the
coefficients move directly from the
C register, bypassing all decimation
registers, and are available at the
output on the following clock cycle.
When decimation is chosen, the
coefficient output is delayed by 1, 2,
or 3 clock cycles depending on how
many decimation registers the
coefficients pass through (D1, D2, or
D3). The number of decimation
registers the coefficients pass
through is determined by DCM
1-0
.
Refer to Table 1 for choosing a
decimation mode.
CIENB enables the C and D registers
for coefficient loading. The registers
are loaded on the rising edge of CLK
when CIENB is LOW. CIENB is
latched and delayed internally which
enables the registers for loading one
clock cycle after CIENB goes active
(loading takes place on the second
rising edge of CLK after CIENB goes
LOW). Therefore, CIENB must be
LOW one clock cycle before the
coefficients are placed on the CIN
8-0
inputs. The coefficients are held when
CIENB is HIGH.
DIENB enables the X register for the
loading of data. The X register is
loaded on the rising edge of CLK
when DIENB is LOW. DIENB is
latched and delayed internally (load-
ing takes place on the second rising
edge of CLK after DIENB goes LOW).
Therefore, DIENB must be LOW one
clock cycle before the data is placed on
the DIN
8-0
inputs. The X register is
loaded with all zeros when DIENB is
HIGH.
The output of the C register (C
8-0
) and
X register (X
8-0
) provide the inputs of
the 9 x 9 multiplier. The multiplier is
followed by two pipeline registers,
D
CELL RESULT
MUX
Q
26
0
18
ZERO
MUX
SIGN
EXTENSION
25-18
17-0
17-0
1
0
26
OUTPUT
BUFFER
25-8
26
1
OUTPUT
MUX
26
0
D
Q
SENBL
SENBH
2
TRI-STATE
BUFFER
26
CLK
RESET.D
TO ALL REGISTERS
TO ALL REGISTERS
M REG0 and M REG1. The output of
the multiplier is sign extended and is
used as one of the inputs to the 26-bit
adder. The output of the 26-bit
accumulator provides the second
input to the adder. Both the accumu-
lator and T register are loaded simul-
taneously with the output of the
adder.
The accumulator is loaded with the
output of the adder on every clock
cycle unless cleared. Clearing the
accumulator can be achieved using
two methods. The first method, when
both RESET and ERASE are LOW,
causes all accumulators and all
registers in the device to be cleared
together. RESET and ERASE are
latched and delayed internally caus-
ing the clearing to occur on the second
clock cycle after RESET and ERASE go
active.
The second method, when only
ERASE is LOW, clears a single accu-
mulator of a selected cell. The cell is
selected using the ADR
2-0
inputs
(decoded to Cell n). ERASE is latched
and delayed internally causing the
clearing to occur on the second clock
cycle after ERASE goes active. Refer
to Table 2 for clearing registers and
accumulators.
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LF43891
DEVICES INCORPORATED
9 x 9-bit Digital Filter
SIGNAL DEFINITIONS
Power
V
CC
and GND
+5 V power supply. All pins must be
connected.
Clock
T
ABLE
1.
DCM1
0
0
1
1
D
ECIMATION
M
ODE
S
ELECTION
Decimation Function
Decimation registers not used
One decimation register used (decimation by one-half)
Two decimation registers used (decimation by one-third)
Three decimation registers used (decimation by one-fourth)
AND
DCM0
0
1
0
1
T
ABLE
2. R
EGISTER
ERASE
0
0
1
1
RESET
0
1
0
1
A
CCUMULATOR
C
LEARING
CLK — Master Clock
The rising edge of CLK strobes all
registers. All timing specifications are
referenced to the rising edge of CLK.
Inputs
DIN
8-0
— Data Input
9-bit data is latched into the X register
of each filter cell simultaneously. The
DIENB signal enables loading of the
data.
CIN
8-0
— Coefficient Input
9-bit coefficients are latched into the C
register of Filter Cell 0. The CIENB
signal enables loading of the coeffi-
cients.
Outputs
SUM
25-0
— Data Output
The 26-bit result from an individual
filter cell will appear when ADR
2-0
is
used to select the filter cell result.
SHADD in conjunction with ADR
2-0
is
used to select the output from the
shift-and-add output stage.
COUT
8-0
— Coefficient Output
The 9-bit coefficient output from
Filter Cell 7 can be connected to the
CIN
8-0
coefficient input of the same
LF43891 to recirculate the coefficients.
COUT
8-0
can also be connected to the
CIN
8-0
of another LF43891 to cascade
the devices. The COENB signal
enables the output of the coefficients.
Clearing Effect
All accumulators and all registers are cleared
Only the accumulator addressed by ADR2-0 is cleared
All registers are cleared (accumulators are not cleared)
No clearing occurs, internal state remains the same
OUTPUT STAGE DESCRIPTION
The 26-bit adder contained in the
output stage can add the contents of
any filter cell accumulator (selected by
ADR
2-0
) with the 18 most significant
bits of the output buffer. The result is
stored back into the output buffer.
The complete operation takes only one
clock cycle. The eight least significant
bits of the output buffer are lost.
The Zero multiplexer is controlled by
the SHADD input signal. This allows
selection of either the 18 most signifi-
cant bits of the output buffer or all
zeros for the adder input. When
SHADD is LOW, all zeros will be
selected. When SHADD is HIGH, the
18 most significant bits of the output
buffer are selected enabling the shift-
and-add operation. SHADD is
latched and delayed internally by one
clock cycle.
The output multiplexer is also con-
trolled by the SHADD input signal.
This allows selection of either a filter
cell accumulator, selected by ADR
2-0
,
or the output buffer to be output to
the SUM
25-0
bus. Only the 26 least
significant bits from either a filter cell
accumulator or the output buffer are
output on SUM
25-0
. If SHADD is
LOW during two consecutive clock
cycles (low during the current and
previous clock cycle), the output
multiplexer selects the contents of a
filter cell accumulator addressed by
ADR
2-0
. Otherwise, the output
multiplexer selects the contents of the
output buffer.
If the same address remains on the
ADR
2-0
inputs for more than one clock
cycle, SUM
25-0
will not change to
reflect any updates to the addressed
cell accumulator. Only the result from
the first selection of the cell (first clock
cycle) will be output. This allows the
interface of slow memory devices
where the output needs to be active
for more than one clock cycle. Normal
FIR operation is not affected because
ADR
2-0
is changed sequentially.
NUMBER SYSTEMS
Data and coefficients can be repre-
sented as either 8-bit unsigned or 9-bit
two's complement numbers. All
values are represented as 9-bit two's
complement numbers internally. If
the most significant or sign bit is a
zero, the multiplier can multiply 8-bit
unsigned numbers.
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LF43891
DEVICES INCORPORATED
9 x 9-bit Digital Filter
DCM
1-0
— Decimation Control
The DCM
1-0
inputs select the num-
ber of decimation registers to use
(Table 1). Coefficients are passed
from one cell to another at a rate
determined by DCM
1-0
. When no
decimation registers are selected,
the coefficients are passed from cell
to cell on every rising edge of CLK
(no decimation). When one decima-
tion register is selected, the coeffi-
cients are passed from cell to cell on
every other rising edge of CLK (2:1
decimation). When two decimation
registers are selected, the coeffi-
cients are passed from cell to cell on
every third rising edge of CLK (3:1
decimation) and so on. DCM
1-0
is
latched and delayed internally.
ADR
2-0
— Cell Accumulator Select
The ADR
2-0
inputs select which cell’s
accumulator will available at the
SUM
25-0
output or added to the
output stage accumulator. In both
cases, ADR
2-0
is latched and delayed
by one clock cycle. If the same
address remains on the ADR
2-0
inputs
for more than one clock cycle,
SUM
25-0
will not change if the con-
tents of the accumulator changes.
Only the result from the first selection
of the cell (first clock cycle) by ADR
2-0
will be available. ADR
2-0
is also used
to select which accumulator to clear
when ERASE is LOW.
SENBH — MSB Output Enable
When SENBH is LOW, SUM
25-16
is
enabled. When SENBH is HIGH,
SUM
25-16
is placed in a high-imped-
ance state.
SENBL — LSB Output Enable
When SENBL is LOW, SUM
15-0
is
enabled. When SENBL is HIGH,
SUM
15-0
is placed in a high-imped-
ance state.
RESET — Register Reset Control
When RESET is LOW, all registers are
cleared simultaneously except the cell
accumulators. RESET can be used
with ERASE to clear all cell accumula-
tors. RESET is latched and delayed
internally. Refer to Table 2.
ERASE — Accumulator Erase Control
When ERASE is LOW, the cell accu-
mulator specified by ADR
2-0
is
cleared. When RESET is LOW in
conjunction with ERASE, all cell
accumulators are cleared. Refer to
Table 2.
Controls
DIENB — Data Input Enable
The DIENB input enables the X
register of every filter cell. While
DIENB is LOW, the X registers are
loaded with the data present at the
DIN
8-0
inputs on the rising edge of
CLK. While DIENB is HIGH, all bits
of DIN
8-0
are forced to zero and a
rising edge of CLK will load the X
register of every filter cell with all
zeros. DIENB must be low one clock
cycle prior to presenting the input
data on the DIN
8-0
input since it is
latched and delayed internally.
CIENB — Coefficient Input Enable
The CIENB input enables the C and D
registers of every filter cell. While
CIENB is LOW, the C and appropriate
D registers are loaded with the
coefficient data on the rising edge of
CLK. While CIENB is HIGH, the
contents of the C and D registers are
held and the CLK signal is ignored.
By using CIENB in its active state,
coefficient data can be shifted from
cell to cell. CIENB must be low one
clock cycle prior to presenting the
coefficient data on the CIN
8-0
input
since it is latched and delayed inter-
nally.
COENB — Coefficient Output Enable
The COENB input enables the
COUT
8-0
output. When COENB is
LOW, the outputs are enabled. When
COENB is HIGH, the outputs are
placed in a high-impedance state.
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