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LF43891JC33

Description
9 x 9-bit Digital Filter
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size100KB,11 Pages
ManufacturerLOGIC Devices
Websitehttp://www.logicdevices.com/
Download Datasheet Parametric Compare View All

LF43891JC33 Overview

9 x 9-bit Digital Filter

LF43891JC33 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerLOGIC Devices
Parts packaging codeLCC
package instructionQCCJ, LDCC84,1.2SQ
Contacts84
Reach Compliance Codecompli
ECCN code3A991.A.2
Other featuresICC SPECIFIED @ 20MHZ
boundary scanNO
maximum clock frequency30.3 MHz
External data bus width9
JESD-30 codeS-PQCC-J84
JESD-609 codee0
length29.3116 mm
low power modeNO
Humidity sensitivity level3
Number of terminals84
Maximum operating temperature70 °C
Minimum operating temperature
Output data bus width26
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Encapsulate equivalent codeLDCC84,1.2SQ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum slew rate160 mA
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width29.3116 mm
uPs/uCs/peripheral integrated circuit typeDSP PERIPHERAL, DIGITAL FILTER
LF43891
DEVICES INCORPORATED
9 x 9-bit Digital Filter
LF43891
DEVICES INCORPORATED
9 x 9-bit Digital Filter
DESCRIPTION
The
LF43891
is a video-speed digital
filter that contains eight filter cells
(taps) cascaded internally and a shift-
and-add output stage. A 9 x 9 multi-
plier, three decimation registers, and a
26-bit accumulator are contained in
each filter cell. The output stage of the
LF43891 contains a 26-bit accumulator
which can add the contents of any
filter stage to the output stage accu-
mulator shifted right by 8 bits. 8-bit
unsigned or 9-bit two’s complement
format for data and coefficients can be
independently selected.
Expanded coefficients and word sizes
can be processed by cascading mul-
tiple LF43891s to implement larger
filter lengths without affecting the
sample rate. By reducing the sample
rate, a single LF43891 can process
larger filter lengths by using multiple
passes. The sampling rate can range
from 0 to 40 MHz. Over 1000 taps
may be processed without overflows
due to the architecture of the device.
The output sample rate can be re-
duced to one-half, one-third, or one-
fourth the input sample rate by using
the three decimation registers con-
tained in every filter cell. Matrix
multiplication, N x N spatial correla-
tions/convolutions, and other 2-D
operations for image processing can
also be achieved using these registers.
FEATURES
u
u
u
u
30 MHz Maximum Sampling Rate
320 MHz Multiply-Accumulate Rate
8 Filter Cells
8-bit Unsigned or 9-bit Two’s
Complement Data/Coefficients
u
26-bit Data Outputs
u
Shift-and-Add Output Stage for
Combining Filter Outputs
u
Expandable Data Size, Coefficient
Size, and Filter Length
u
User-Selectable 2:1, 3:1, or 4:1
Decimation
u
Replaces Harris HSP43891
u
84-pin PLCC, J-Lead
LF43891 B
LOCK
D
IAGRAM
DIN
8-0
9
DIENB, CIENB,
ERASE, DCM
1-0
5
CIN
8-0
9
FILTER
CELL 0
9
FILTER
CELL 1
9
FILTER
CELL 2
9
FILTER
CELL 3
9
FILTER
CELL 4
9
FILTER
CELL 5
9
FILTER
CELL 6
9
FILTER
CELL 7
9
COUT
8-0
ADR
2-0
3
26
26
26
26
26
26
26
26
COENB
MUX
26
SHADD
SENBL
SENBH
RESET
26
OUTPUT
STAGE
TO ALL CELLS
CLK
TO ALL REGISTERS
SUM
25-0
Video Imaging Products
1
08/16/2000–LDS.43891-J

LF43891JC33 Related Products

LF43891JC33 LF43891JC40 LF43891
Description 9 x 9-bit Digital Filter 9 x 9-bit Digital Filter 9 x 9-bit Digital Filter
Is it Rohs certified? incompatible incompatible -
Maker LOGIC Devices LOGIC Devices -
Parts packaging code LCC LCC -
package instruction QCCJ, LDCC84,1.2SQ QCCJ, LDCC84,1.2SQ -
Contacts 84 84 -
Reach Compliance Code compli compli -
Other features ICC SPECIFIED @ 20MHZ ICC SPECIFIED @ 20MHZ -
boundary scan NO NO -
maximum clock frequency 30.3 MHz 25 MHz -
External data bus width 9 9 -
JESD-30 code S-PQCC-J84 S-PQCC-J84 -
JESD-609 code e0 e0 -
length 29.3116 mm 29.3116 mm -
low power mode NO NO -
Humidity sensitivity level 3 3 -
Number of terminals 84 84 -
Maximum operating temperature 70 °C 70 °C -
Output data bus width 26 26 -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code QCCJ QCCJ -
Encapsulate equivalent code LDCC84,1.2SQ LDCC84,1.2SQ -
Package shape SQUARE SQUARE -
Package form CHIP CARRIER CHIP CARRIER -
Peak Reflow Temperature (Celsius) 225 225 -
power supply 5 V 5 V -
Certification status Not Qualified Not Qualified -
Maximum seat height 5.08 mm 5.08 mm -
Maximum slew rate 160 mA 160 mA -
Maximum supply voltage 5.25 V 5.25 V -
Minimum supply voltage 4.75 V 4.75 V -
Nominal supply voltage 5 V 5 V -
surface mount YES YES -
technology CMOS CMOS -
Temperature level COMMERCIAL COMMERCIAL -
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) -
Terminal form J BEND J BEND -
Terminal pitch 1.27 mm 1.27 mm -
Terminal location QUAD QUAD -
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED -
width 29.3116 mm 29.3116 mm -
uPs/uCs/peripheral integrated circuit type DSP PERIPHERAL, DIGITAL FILTER DSP PERIPHERAL, DIGITAL FILTER -
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