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LF3320QC12

Description
Horizontal Digital Image Filter
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size582KB,24 Pages
ManufacturerLOGIC Devices
Websitehttp://www.logicdevices.com/
Download Datasheet Parametric Compare View All

LF3320QC12 Overview

Horizontal Digital Image Filter

LF3320QC12 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerLOGIC Devices
Parts packaging codeQFP
package instructionQFP, QFP144,1.2SQ
Contacts144
Reach Compliance Codecompli
ECCN code3A001.A.3
boundary scanNO
maximum clock frequency83 MHz
External data bus width12
JESD-30 codeS-PQFP-G144
JESD-609 codee0
length28 mm
low power modeNO
Humidity sensitivity level3
Number of terminals144
Maximum operating temperature70 °C
Minimum operating temperature
Output data bus width16
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP144,1.2SQ
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply3.3 V
Certification statusNot Qualified
Maximum seat height4.0995 mm
Maximum slew rate190 mA
Maximum supply voltage3.6 V
Minimum supply voltage3 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width28 mm
uPs/uCs/peripheral integrated circuit typeDSP PERIPHERAL, DIGITAL FILTER
LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
LF3320
DEVICES INCORPORATED
Horizontal Digital Image Filter
DESCRIPTION
The
LF3320
filters digital images in the
horizontal dimension at real-time
video rates. The input and coefficient
data are both 12 bits and in two’s
complement format. The output is also
in two’s complement format and may
be rounded to 16 bits.
The LF3320 is designed to take
advantage of symmetric coefficient
sets. When symmetric coefficient sets
are used, the device can be configured
as a single 32-tap FIR filter or as two
separate 16-tap FIR filters.
When asymmetric coefficient sets are
used, the device can be configured as a
single 16-tap FIR filter or as two
separate 8-tap FIR filters. Multiple
LF3320s can be cascaded to create
larger filters.
Interleave/Decimation Registers (I/D
Registers) allow interleaved data to be
fed directly into the device and filtered
without separating the data into
individual data streams.
The LF3320 can handle a maximum of
sixteen data sets interleaved together.
The I/D Registers and on-chip accu-
mulators facilitate using decimation to
increase the number of filter taps.
Decimation of up to 16:1 is supported.
The LF3320 contains enough on-board
memory to store 256 coefficient sets.
Two separate LF Interfaces
TM
allow all
256 coefficient sets to be updated within
vertical blanking.
FEATURES
83 MHz Data Rate
12-bit Data or Coefficients (Expand-
able to 24-bit)
32-Tap FIR Filter, Cascadable for
More Filter Taps
Over 49 K-bits of on-board Memory
LF Interface
TM
Allows All 256
Coefficient Sets to be Updated
Within Vertical Blanking
Various Operating Modes: Dual
Filter, Single Filter, Double Wide
Data or Coefficient, Matrix Multipli-
cation, and Accumulator Access.
Selectable 16-bit Data Output with
User-Defined Rounding and Limiting
Supports Interleaved Data Streams
Supports Decimation up to 16:1 for
Increasing Number of Filter Taps
3.3 Volt Supply
144 Lead PQFP
LF3320 B
LOCK
D
IAGRAM
ROUT
11-0
12
12
RIN
11-0
DIN
11-0
CAA
7-0
CENA
CFA
11-0
PAUSEA
LDA
12
INTERLEAVE / DECIMATION
REGISTERS
12
COUT
11-0
CAB
7-0
8
8
CENB
12
256
COEFFICIENT
SET
STORAGE
16-TAP
FILTER A
16-TAP
FILTER B
256
COEFFICIENT
SET
STORAGE
12
CFB
11-0
PAUSEB
LDB
ROUND
SELECT
LIMIT
CIRCUITRY
CLK
OED
16
DOUT
15-0
Video Imaging Products
2-1
08/16/2000–LDS.3320-N

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