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LF2249QC25

Description
12 x 12-bit Digital Mixer
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size84KB,8 Pages
ManufacturerLOGIC Devices
Websitehttp://www.logicdevices.com/
Download Datasheet Parametric Compare View All

LF2249QC25 Overview

12 x 12-bit Digital Mixer

LF2249QC25 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerLOGIC Devices
Parts packaging codeQFP
package instructionQFP, QFP120,1.2SQ,32
Contacts120
Reach Compliance Codecompli
ECCN code3A991.A.2
Other features4 X 12 BIT DATA INPUT BUS; 16 BIT CASCADE DATA INPUT; ICC SPECIFIED @ 25MHZ
boundary scanNO
maximum clock frequency40 MHz
External data bus width12
JESD-30 codeS-PQFP-G120
JESD-609 codee0
length28 mm
low power modeNO
Humidity sensitivity level3
Number of terminals120
Maximum operating temperature70 °C
Minimum operating temperature
Output data bus width16
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Encapsulate equivalent codeQFP120,1.2SQ,32
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)225
power supply5 V
Certification statusNot Qualified
Maximum seat height4.1 mm
Maximum slew rate100 mA
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width28 mm
uPs/uCs/peripheral integrated circuit typeDSP PERIPHERAL, MIXER
LF2249
DEVICES INCORPORATED
12 x 12-bit Digital Mixer
LF2249
DEVICES INCORPORATED
12 x 12-bit Digital Mixer
DESCRIPTION
The
LF2249
is a high-speed digital
mixer comprised of two 12-bit
multipliers and a 24-bit accumulator.
All multiplier inputs are user acces-
sible, and each can be updated on
every clock cycle. The LF2249 utilizes
a pipelined architecture with fully
registered inputs and outputs and an
asynchronous three-state output
enable control for optimum flexibility.
Independent input register clock
enables allow the user to hold the
data inputs over multiple clock cycles.
Each multiplier input also includes a
user-selectable 1-16 clock pipeline
delay. The output of each multiplier
can be independently negated under
user control for subtraction of prod-
ucts. The sum of the products can
also be internally rounded to 16 bits
during the accumulation process.
A separate 16-bit input port con-
nected to the accumulator is included
to allow cascading of multiple
LF2249s. Access to all 24 bits of the
accumulator is gained by switching
between upper or lower 16-bit words.
The accumulated output data is
updated on every clock cycle.
All inputs and outputs of the LF2249
are registered on the rising edge of
clock, except for OE. Internal pipeline
registers for all data and control
inputs are provided to maintain
FEATURES
u
40 MHz Data and Computation Rate
u
Two 12 x 12-bit Multipliers with
Individual Data Inputs
u
Separate 16-bit Input Port for
Cascading Devices
u
Independent, User-Selectable 1–16
Clock Pipeline Delay for Each Data
Input
u
User-Selectable Rounding of Products
u
Fully Registered, Pipelined
Architecture
u
Three-State Outputs
u
Fully TTL Compatible
u
Replaces TRW/Raytheon/Fairchild
TMC2249
u
120-pin PQFP
1
2
3
4
5
6
LF2249 B
LOCK
D
IAGRAM
ADEL
3-0
A
11-0
ENA
BDEL
3-0
B
11-0
ENB
CDEL
3-0
C
11-0
ENC
DDEL
3-0
D
11-0
END
7
8
1–16
1–16
1–16
1–16
9
4
NEG
2
CLK
NEG
1
4
10
RND
4
2's COMP
2's COMP
4
ACC
11
FT
16
3
CASEN
2:1
16
24
CAS
15-0
MS
1
16
0
0
16
1
LS
SWAP
2:1
2:1
OE
16
NOTE: NUMBERS IN REGISTERS INDICATED
NUMBER OF PIPELINE DELAYS.
S
15-0
Video Imaging Products
1
08/16/2000–LDS.2249-J

LF2249QC25 Related Products

LF2249QC25 LF2249 LF2249QC33
Description 12 x 12-bit Digital Mixer 12 x 12-bit Digital Mixer 12 x 12-bit Digital Mixer
Is it Rohs certified? incompatible - incompatible
Maker LOGIC Devices - LOGIC Devices
Parts packaging code QFP - QFP
package instruction QFP, QFP120,1.2SQ,32 - QFP, QFP120,1.2SQ,32
Contacts 120 - 120
Reach Compliance Code compli - compli
ECCN code 3A991.A.2 - 3A991.A.2
Other features 4 X 12 BIT DATA INPUT BUS; 16 BIT CASCADE DATA INPUT; ICC SPECIFIED @ 25MHZ - 4 X 12 BIT DATA INPUT BUS; 16 BIT CASCADE DATA INPUT; ICC SPECIFIED @ 25MHZ
boundary scan NO - NO
maximum clock frequency 40 MHz - 30.33 MHz
External data bus width 12 - 12
JESD-30 code S-PQFP-G120 - S-PQFP-G120
JESD-609 code e0 - e0
length 28 mm - 28 mm
low power mode NO - NO
Humidity sensitivity level 3 - 3
Number of terminals 120 - 120
Maximum operating temperature 70 °C - 70 °C
Output data bus width 16 - 16
Package body material PLASTIC/EPOXY - PLASTIC/EPOXY
encapsulated code QFP - QFP
Encapsulate equivalent code QFP120,1.2SQ,32 - QFP120,1.2SQ,32
Package shape SQUARE - SQUARE
Package form FLATPACK - FLATPACK
Peak Reflow Temperature (Celsius) 225 - 225
power supply 5 V - 5 V
Certification status Not Qualified - Not Qualified
Maximum seat height 4.1 mm - 4.1 mm
Maximum slew rate 100 mA - 100 mA
Maximum supply voltage 5.25 V - 5.25 V
Minimum supply voltage 4.75 V - 4.75 V
Nominal supply voltage 5 V - 5 V
surface mount YES - YES
technology CMOS - CMOS
Temperature level COMMERCIAL - COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) - Tin/Lead (Sn/Pb)
Terminal form GULL WING - GULL WING
Terminal pitch 0.8 mm - 0.8 mm
Terminal location QUAD - QUAD
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED
width 28 mm - 28 mm
uPs/uCs/peripheral integrated circuit type DSP PERIPHERAL, MIXER - DSP PERIPHERAL, MIXER
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Index Files: 814  21  1996  513  759  17  1  41  11  16 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
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