Low Capacitance TVS Diode Array
For Multi-mode Tranciever Protection
PROTECTION PRODUCTS
Description
The LCDA15C-6 has been specifically designed to
protect sensitive components which are connected to
data and transmission lines from over voltages caused
by
ESD
(electrostatic discharge),
EFT
(electrical fast
transients), and
lightning.
The low capacitance array configuration of the
LCDA15C-6 allows the user to protect six high-speed
data or I/O lines. They may be used on systems
operating from 5 to 15 Volts. The high surge capability
(500W, tp=8/20µs) makes the LCDA15C-6 suitable for
telecommunications systems operating in harsh tran-
sient environments. The low inductance construction
minimizes voltage overshoot during high current
surges.
The features of the LCDA15C-6 are ideal for protecting
multi-protocol transceivers in WAN applications such as
Frame Relay systems, routers, and switches.
LCDA15C-6
Features
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Transient protection for high-speed data lines to
IEC 61000-4-2 (ESD) 15kV (air), 8kV (contact)
IEC 61000-4-4 (EFT) 40A (5/50ns)
IEC 61000-4-5 (Lightning) 0.5kV, 12A (8/20µs)
Protects six I/O lines
Low capacitance for high-speed interfaces
High surge capability
Low clamping voltage
Solid-state silicon avalanche technology
JEDEC SO-8 package
Molding compound flammability rating: UL 94V-0
Marking : Part number, date code, logo
Packaging : Tape and Reel per EIA 481
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Mechanical Characteristics
Applications
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Multi-Mode Transceiver Protection
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WAN Equipment:
CSU/DSU
Multiplexers
Routers
ISP Equipment
Customer Premise Equipment
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Protection for any of the following interfaces:
RS-232 (V.28)
RS-422 (V.11, X.21)
RS-449 (V.11/V.10)
RS-485
Circuit Diagram
Schematic & PIN Configuration
SO-8 (Top View)
Revision 9/2000
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LCDA15C-6
PROTECTION PRODUCTS
Absolute Maximum Rating
R ating
Peak Pulse Pow er (tp = 8/20µ s)
Peak Pulse Current (tp = 8/20µ s)
Lead Sold ering Temp erature
Op erating Temp erature
Storage Temp erature
Symbo l
P
p k
I
PP
T
L
T
J
T
STG
Value
500
15
260 (10 sec.)
-55 to +125
-55 to +150
Units
Watts
A
°C
°C
°C
Electrical Characteristics
LCDA15C-6
Par ame te r
Reverse Stand -Off Voltage
Reverse Breakd ow n Voltage
Reverse Leakage Current
Clamp ing Voltage
Clamp ing Voltage
Junction Cap acitance
Symbo l
V
RWM
V
BR
I
R
V
C
V
C
C
j
I
t
= 1mA
V
RWM
= 15V, T=25°C
I
PP
= 1A , tp = 8/20µ s
I
PP
= 15A , tp = 8/20µ s
Betw een I/O p ins and
Gnd
V
R
= 0V, f = 1MHz
Betw een I/O p ins
V
R
= 0V, f = 1MHz
8
16.7
5
24
33
15
Co nd itio ns
Minimum
Typ ical
Maximum
15
Units
V
V
µA
V
V
pF
3
pF
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LCDA15C-6
PROTECTION PRODUCTS
Typical Characteristics
Non-Repetitive Peak Pulse Power vs. Pulse Time
10
110
100
Peak Pulse Power - P
PP
(kW)
90
% of Rated Power or I
PP
80
70
60
50
40
30
20
10
0.01
0.1
1
10
Pulse Duration - tp (µs)
100
1000
0
0
25
50
75
100
125
o
Power Derating Curve
1
0.1
150
175
Ambient Temperature - T
A
( C)
Pulse Waveform
110
100
90
80
Percent of I
PP
70
60
50
40
30
20
10
0
0
5
10
15
Time (µs)
20
25
30
td = I
PP
/2
e
-t
Clamping Voltage vs. Peak Pulse Current
28
Waveform
Parameters:
tr = 8µs
td = 20µs
26
Clamping Voltage - V
C
(V)
24
22
20
18
16
14
12
10
0
2
4
6
8
10
12
14
16
Peak Pulse Current - I
PP
(A)
Waveform
Parameters:
tr = 8µs
td = 20µs
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LCDA15C-6
PROTECTION PRODUCTS
Applications Information
Device Connection Options for Protection of Six High-
Speed Data Lines
The LCDA16C-6 may be configured to protect up to six
I/O lines operating between 5 and 15V. It may be used
to protect the most popular serial data interface
standard lines making it ideal for use in equipment
utilizing multi-mode transceivers. Data lines are
connected at pins 1, 2, 3, 6, 7, and 8. Pins 4 and 5
are connected to ground. For best results, these pins
should be connected directly to a ground plane on the
board. The path length should be kept as short as
possible to minimize parasitic inductance.
Multi-Mode Transceiver Protection
A typical multi-mode transceiver protection circuit is
shown. The LCDA15C-6 is used to protect I/O lines
with external connections. The LCDA15C-6 adds a
maximum loading capacitance of 15pF with a working
voltage of 15V. This allows the transceiver to safely
operate in all modes without clipping or degradation of
the signal.
With proper design and layout, the transceiver port can
be protected to >15kV (HBM per IEC 61000-4-2).
Circuit Board Layout Recommendations for Suppres-
sion of ESD.
Good circuit board layout is critical for the suppression
of fast rise-time transients such as ESD. The following
guidelines are recommended:
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Place the LCDA15C-6 near the input terminals or
connectors to restrict transient coupling.
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Minimize the path length between the LCDA15C-6
and the protected line.
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Minimize all conductive loops including power and
ground loops.
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The ESD transient return path to ground should be
kept as short as possible.
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Never run critical signals near board edges.
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Use ground planes whenever possible.
Multi-Mode Tranceiver Protection Example
Device Connection
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LCDA15C-6
PROTECTION PRODUCTS
Outline Drawing - SO-8
Land Pattern - SO-8
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