Ordering number : ENN*6695
CMOS IC
LC863332/28/24/20/16A
8-Bit Single Chip Microcontroller
Preliminary
Overview
The LC863332/28/24/20/16A are 8-bit single chip microcontrollers with the following on-chip functional blocks:
- CPU : Operable at a minimum bus cycle time of 0.424µs
- On-chip ROM capacity
Program ROM : 32K/28K/24K/20K/16K bytes
CGROM : 16K bytes
- On-chip RAM capacity : 512 bytes
- OSD RAM : 352
×
9 bits
- Five channels
×
8-bit AD Converter
- Three channels
×
7-bit PWM
- Two 16-bit timer/counters, 14-bit base timer
- 8-bit synchronous serial interface circuit
- IIC-bus compliant serial interface circuit (Multi-master type)
- ROM correction function
- 15-source 9-vectored interrupt system
- Integrated system clock generator and display clock generator
X’tal oscillator (32.768kHz) for PLL reference is used for TV control.
All of the above functions are fabricated on a single chip.
Ver.1.01
N1798
91400 RM (IM) HS No.6695-1/20
LC863332/28/24/20/16A
Features
(1) Read-Only Memory (ROM) :
32768
×
8 bits / 28672
×
8 bits / 24576
×
8 bits
20480
×
8 bits / 16384
×
8 bits for program
16128
×
8 bits for CGROM
512
×
8 bits (including 128 bytes for ROM correction function)
352
×
9 bits (for CRT display)
(2) Random Access Memory (RAM) :
(3) OSD functions
- Screen display
: 36 characters
×
16 lines (by software)
- RAM
: 352 words (9 bits per word)
Display area
: 36 words
×
8 lines
Control area
: 8 words
×
8 lines
- Characters
Up to 252 kinds of 16
×
32 dot character fonts
(4 characters including 1 test character are not programmable)
Each font can be divided into two parts and used as two fonts :
a 16
×
17 dot and 8
×
9 dot character font
- Various character attributes
Character colors
: 16 colors
Character background colors
: 16 colors
Fringe / shadow colors
: 16 colors
Full screen colors
: 16colors
Rounding
Underline
Italic character (slanting)
- Attribute can be changed without spacing
- Vertical display start line number can be set for each row independently (Rows can be overlapped)
- Horizontal display start position can be set for each row independently
- Horizontal pitch (bit 9 - 16)
*1
and vertical pitch (bit-32) can be set for each row independently
- Different display modes can be set for each row independently
Caption • Text mode / OSD mode 1 / OSD mode 2 (Quarter size) / Simplifed graphic mode
- Ten character sizes
*1
Horez.
×
Vert. = (1
×
1), (1
×
2), (2
×
2), (2
×
4), (0.5
×
0.5)
(1.5
×
1), (1.5
×
2), (3
×
2), (3
×
4), (0.75
×
0.5)
- Shuttering and scrolling on each row
- Simplified Graphic Display
*1 Note : range depends on display mode : refer to the manual for details.
(4) Bus Cycle Time / Instruction-Cycle Time
Bus cycle time
0.424µs
7.5µs
183.1µs
Instruction cycle time
0.848µs
15.0µs
366.2µs
System clock oscillation
Internal VCO
(Ref : X’tal 32.768kHz)
Internal RC
Crystal
Oscillation Frequency
14.156MHz
800kHz
32.768kHz
Voltage
4.5V to
5.5V
4.5V to
5.5V
4.5V to
5.5V
(5) Ports
- Input / Output Ports
: 5 ports (28 terminals)
Data direction programmable in nibble units
: 1 port (8 terminals)
(If the N-ch open drain output is selected by option, the corresponding port data can be read in output mode.)
Data direction programmable for each bit individually
: 4 ports (20 terminals)
- Input port
: 1 port (1 terminal)
No.6695-2/20
LC863332/28/24/20/16A
(6) AD converter
- 5 channels
×
8-bit AD converters
(7) Serial interfaces
- IIC-bus compliant serial interface (Multi-master type)
Consists of a single built-in circuit with two I/O channels.
internally.
- Synchronous 8-bit serial interface
(8) PWM output
- 3 channels
×
7-bit PWM
(9) Timer
- Timer 0 : 16-bit timer/counter
With 2-bit prescaler + 8-bit programmable prescaler
Mode 0 : Two 8-bit timers with a programmable prescaler
Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter
Mode 2 : 16-bit timer with a programmable prescaler
Mode 3 : 16-bit counter
The resolution of timer is 1 tCYC.
- Timer 1 : 16-bit timer/PWM
Mode 0 : Two 8-bit timers
Mode 1 : 8-bit timer + 8-bit PWM
Mode 2 : 16-bit timer
Mode 3 : Variable bit PWM (9 to 16 bits)
In mode0/1,the resolution of Timer1/PWM is 1 tCYC
In mode2/3,the resolution is selectable by program; tCYC or 1/2 tCYC
- Base timer
Generate every 500ms overflow for a clock application (using 32.768kHz crystal oscillation for the base timer clock)
Generate every 976µs, 3.9ms, 15.6ms, 62.5ms overflow (using 32.768kHz crystal oscillation for the base timer
clock)
Clock for the base timer is selectable from 32.768kHz crystal oscillation, system clock or programmable prescaler
output of Timer 0
(10) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal)
- Noise rejection function
- Polarity switching
(11) Watchdog timer
External RC circuit is required
Interrupt or system reset is activated when the timer overflows
(12) ROM correction function
Max 128 bytes / 2 addresses
(13) Interrupts
- 15 sources 9 vectored interrupts
1. External Interrupt INT0
2. External Interrupt INT1
3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits)
4. External Interrupt INT3, base timer
5. Timer/counter T0H (Upper 8 bits)
6. Timer T1H,T1L
7. SIO0
8. Vertical synchronous signal interrupt ( VS ), horizontal line (
HS
), AD
9. IIC, Port 0
The two data lines and two clock lines can be connected
No.6695-3/20
LC863332/28/24/20/16A
- Interrupt priority control
Three interrupt priorities are supported (low, high and highest) and multi-level nesting is possible. Low or high
priority can be assigned to the interrupts from 3 to 9 listed above. For the external interrupt INT0 and INT1, high
or highest priority can be set.
(14) Sub-routine stack level
- A maximum of 128 levels (stack is built in the internal RAM)
(15) Multiplication/division instruction
- 16 bits
×
8 bits (7 instruction cycle times)
- 16 bits / 8 bits (7 instruction cycle times)
(16) 3 oscillation circuits
- Built-in RC oscillation circuit used for the system clock
- Built-in VCO circuit used for the system clock and OSD
- X’tal oscillation circuit used for base timer, system clock and PLL reference
(17) Standby function
- HALT mode
The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is
stopped. This mode can be released by the interrupt request or the system reset.
- HOLD mode
The HOLD mode is used to stop the oscillations; RC (internal), VCO, and X’tal oscillations. This mode can be
released by the following conditions.
• Pull the reset terminal ( RES ) to low level.
• Feed the selected level to either P70/INT0 or P71/INT1.
• Input the interrupt condition to Port 0.
(18) Package
- DIP42S
- QIP48E
(19) Development tools
- Flash EEPROM:
- Evaluation chip:
- Emulator:
LC86F3348A
LC863096
EVA86000 (main) + ECB863200 (evaluation chip board)
+ POD863300 (pod: DIP42S) or POD863301 (QIP48E)
No.6695-4/20
LC863332/28/24/20/16A
System Block Diagram
Interrupt Control
IR
PLA
Standby Control
ROM
RC
VCO
Clock
Generator
X’tal
PC
PLL
IIC
ROM Correct Control
ACC
SIO0
XRAM
B Register
Timer 0
Bus Interface
C Register
Timer 1
Port 1
ALU
Base Timer
Port 6
ADC
Port 7
PSW
INT0-3
Noise Rejection Filter
Port 8
RAR
PWM
CGROM
OSD
Control
Circuit
RAM
Stack Pointer
VRAM
Port 0
Watch Dog Timer
No.6695-5/20
FPGA/CPLD
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