INTEGRATED CIRCUITS
DATA SHEET
TZA3012AHW
30 Mbits/s up to 3.2 Gbits/s
A-rate™ fibre optic receiver
Product specification
Supersedes data of 2002 Sep 10
2003 May 21
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate™ fibre optic receiver
FEATURES
•
Single 3.3 V power supply
•
I
2
C-bus and pin programmable fibre optic receiver.
Dual limiter features
•
Dual limiting input with 12 mV sensitivity
•
Received Signal Strength Indicator (RSSI)
•
Loss Of Signal (LOS) indicator with threshold adjust
•
Differential overvoltage protection.
Data and clock recovery features
•
Supports SHD/SONET bit rates at 155.52, 622.08,
2488.32 and 2666.06 Mbits/s (STM16/OC48
+
FEC)
•
Supports Gigabit Ethernet at 1250 and 3125 Mbits/s
•
Supports Fibre Channel at 1062.5 and 2125 Mbits/s
•
ITU-T compliant jitter tolerance
•
Frequency lock indicator
•
Stable clock signal when input data absent
•
Outputs for recovered data and clock loop mode.
Demultiplexer features
•
1:16, 1:10, 1:8 or 1:4 demultiplexing ratio
•
LVPECL or CML demultiplexer outputs
•
Frame detection for SDH/SONET and GE frames
•
Parity bit generation
•
Loop mode inputs to demultiplexer.
Additional features with the I2C-bus
•
A-rate
TM(1)
supports any bit rate from 30 Mbits/s to
3.2 Gbits/s with one reference frequency
•
Programmable frequency resolution of 10 Hz
•
Four reference frequency ranges
•
Adjustable swing of data, clock and parallel outputs
•
Programmable polarity of all RF I/Os
(1) A-rate is a Trademark of Koninklijke Philips Electronics N.V.
TZA3012AHW
•
Exchangeable pin designations of RF clock with data for
all I/Os for optimum connectivity
•
Reversible pin designations of parallel data bus bits for
optimum connectivity
•
Slice level adjustment to improve Bit Error Rate (BER)
•
Mute function for a forced logic 0 output state
•
Programmable parity
•
Programmable 32-bit frame detection.
APPLICATIONS
•
Any optical transmission system with bit rates between
30 Mbits/s and 3.2 Gbits/s
•
Physical interface IC in receive channels
•
Transponder applications
•
Dense Wavelength Division Multiplexing (DWDM)
systems.
GENERAL DESCRIPTION
The TZA3012AHW is a fully integrated optical network
receiver containing a dual limiter, Data and Clock
Recovery (DCR) and a demultiplexer with demultiplexing
ratios 1:16, 1:10, 1:8 or 1:4.
The A-rate feature allows the IC to operate at any bit rate
between 30 Mbits/s and 3.2 Gbits/s using a single
reference frequency. The receiver supports loop modes
with serial clock and data inputs and outputs. All clock
signals are generated using a fractional N synthesizer with
10 Hz resolution giving a true, continuous rate operation.
For full configuration flexibility, the receiver is
programmable by pin or via the I
2
C-bus.
ORDERING INFORMATION
TYPE
NUMBER
TZA3012AHW
PACKAGE
NAME
HTQFP100
DESCRIPTION
plastic thermal enhanced thin quad flat package; 100 leads;
body 14
×
14
×
1 mm; exposed die pad
VERSION
SOT638−1
2003 May 21
2
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DLOOPQ CLOOPQ
LOS1
5
38
39
PARITY
PARITYQ
87
88 84 85
91
52 30 31
DLOOP
ENLINQ
pagewidth
CLOOP
ENBA
DMXR1
DMXR0
2003 May 21
6
LOS
RSSI1
BLOCK DIAGRAM
Philips Semiconductors
LOSTH1
7
RSSI
INSEL
12
IN1
d
9
TZA3012AHW
c
16
D00
to D15
44, 46, 48, 53
55, 57, 59, 61,
64, 66, 68, 70
72, 77, 79, 81
IN1Q
SWITCH
PHASE
2
DETECTOR
d
c
16
2
2
2
41
42
36
37
94
95
10
LIM
30 Mbits/s up to 3.2 Gbits/s
A-rate™ fibre optic receiver
16
DMX
1 : 4
16
1:8
1 : 10
1 : 16
45, 47, 49, 54
56, 58, 60, 62,
65, 67, 69, 71
73, 78, 80, 82
D00Q
to D15Q
POCLK
POCLKQ
FP
FPQ
COUT
COUTQ
PARITY
GENERATOR
AND
BUS SWAP
IN2
17
LIM
IN2Q
LPF
LOS
FREQUENCY
WINDOW DETECTOR
RSSI
3
20
LOS2
CREF
WINSIZE
INWINDOW
PRSCLO
ENLOUTQ
CREFQ
PRSCLOQ
21
13 33 34 27 2
3
90
13
VDD
VCCD
VCCO
1, 35, 40, 43, 51
75, 76, 83, 86,
89, 93, 96, 99
32
25
LOSTH2
19
SCL(DR2)
24
97
98
INTERRUPT
CONTROLLER
92
SDA(DR1)
23
CS(DR0)
22
I
2
C-BUS
UI
4
DOUT
DOUTQ
INT
i.c.
2
28, 29
RREF
14
8, 11,
15, 18
26, 50, 63,
74, 100
MGU314
4
RSSI2
VCCA
VEE
LIM = Limiting amplifier.
RSSI = Receiving Signal Strength Indicator.
LOS = Loss Of Signal detector.
LPF = Low-Pass Filter.
DMX = Demultiplexer.
TZA3012AHW
Product specification
Fig.1 Simplified block diagram.
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate™ fibre optic receiver
PINNING
SYMBOL
V
EE
V
CCD
PRSCLO
PRSCLOQ
UI
LOS1
RSSI1
LOSTH1
V
CCA
IN1
IN1Q
V
CCA
INSEL
WINSIZE
RREF
V
CCA
IN2
IN2Q
V
CCA
LOSTH2
RSSI2
LOS2
CS(DR0)
SDA(DR1)
SCL(DR2)
V
DD
V
EE
INWINDOW
i.c.
i.c.
DMXR0
DMXR1
2003 May 21
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DESCRIPTION
supply voltage (digital part)
prescaler output
prescaler inverted output
user interface select
first input channel loss of signal
output
first input channel received
signal strength indicator output
first input channel loss of signal
threshold input
supply voltage (analog part)
first channel input
first channel inverted input
supply voltage (analog part)
input selector
wide and narrow frequency
detect window select
reference resistor input
supply voltage (analog part)
second channel input
second channel inverted input
supply voltage (analog part)
second input channel loss of
signal threshold input
second input channel received
signal strength indicator output
LOS output of second input
channel
chip select (data rate select 0)
I
2
C-bus serial data (data rate
select 1)
I
2
C-bus serial clock (data rate
select 2)
supply voltage (digital part)
ground
frequency window detector
output
internally connected
internally connected
demultiplexing ratio select 0
demultiplexing ratio select 1
4
SYMBOL
V
CCO
CREF
CREFQ
V
CCD
FP
FPQ
PARITY
PARITYQ
V
CCD
POCLK
POCLKQ
V
CCD
D00
D00Q
D01
D01Q
D02
D02Q
V
EE
V
CCD
ENBA
D03
D03Q
D04
D04Q
D05
D05Q
D06
D06Q
D07
D07Q
V
EE
D08
D08Q
D09
D09Q
D10
D10Q
D11
D11Q
D12
die pad common ground plane
PIN
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
TZA3012AHW
DESCRIPTION
supply voltage (clock generator)
reference clock input
reference clock inverted input
supply voltage (digital part)
frame pulse output
frame pulse inverted output
parity output
parity inverted output
supply voltage (digital part)
parallel clock output
parallel clock inverted output
supply voltage (digital part)
parallel data 00 output
parallel data 00 inverted output
parallel data 01 output
parallel data 01 inverted output
parallel data 02 output
parallel data 02 inverted output
ground
supply voltage (digital part)
byte alignment enable input
parallel data 03 output
parallel data 03 inverted output
parallel data 04 output
parallel data 04 inverted output
parallel data 05 output
parallel data 05 inverted output
parallel data 06 output
parallel data 06 inverted output
parallel data 07 output
parallel data 07 inverted output
ground
parallel data 08 output
parallel data 08 inverted output
parallel data 09 output
parallel data 09 inverted output
parallel data 10 output
parallel data 10 inverted output
parallel data 11 output
parallel data 11 inverted output
parallel data 12 output
Philips Semiconductors
Product specification
30 Mbits/s up to 3.2 Gbits/s
A-rate™ fibre optic receiver
SYMBOL
D12Q
V
EE
V
CCD
V
CCD
D13
D13Q
D14
D14Q
D15
D15Q
V
CCD
CLOOP
CLOOPQ
V
CCD
DLOOP
DLOOPQ
V
CCD
PIN
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
ground
supply voltage (digital part)
supply voltage (digital part)
parallel data 13 output
parallel data 13 inverted output
parallel data 14 output
parallel data 14 inverted output
parallel data 15 output
parallel data 15 inverted output
supply voltage (digital part)
loop mode clock input
loop mode clock inverted input
supply voltage (digital part)
loop mode data input
loop mode data inverted input
supply voltage (digital part)
INT
V
CCD
COUT
COUTQ
V
CCD
DOUT
DOUTQ
V
CCD
V
EE
92
93
94
95
96
97
98
99
100
ENLINQ
91
DESCRIPTION
parallel data 12 inverted output
SYMBOL
ENLOUTQ
PIN
90
TZA3012AHW
DESCRIPTION
line loop back enable input
(active LOW)
diagnostic loop back enable
input (active LOW)
interrupt output
supply voltage (digital part)
recovered clock output
recovered clock inverted output
supply voltage (digital part)
recovered data output
recovered data inverted output
supply voltage (digital part)
ground
2003 May 21
5
stm32/stm8
京公网安备 11010802033920号
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