NCV4269C
5.0 V Micropower 150 mA
LDO Linear Regulator with
DELAY, Adjustable RESET,
and Sense Output
The NCV4269C is a 5.0 V precision micropower voltage regulator
with an output current capability of 150 mA.
The output voltage is accurate within
±2.0%
with a maximum
dropout voltage of 0.5 V at 100 mA. Low quiescent current is a feature
drawing only 125
mA
with a 1.0 mA load. This part is ideal for any and
all battery operated microprocessor equipment.
Microprocessor control logic includes an active reset output RO
with delay and a SI/SO monitor which can be used to provide an early
warning signal to the microprocessor of a potential impending reset
signal. The use of the SI/SO monitor allows the microprocessor to
finish any signal processing before the reset shuts the microprocessor
down.
The active Reset circuit operates correctly at an output voltage as
low as 1.0 V. The Reset function is activated during the power up
sequence or during normal operation if the output voltage drops
outside the regulation limits.
The reset threshold voltage can be decreased by the connection of an
external resistor divider to the R
ADJ
lead. The regulator is protected
against reverse battery, short circuit, and thermal overload conditions.
The device can withstand load dump transients making it suitable for
use in automotive environments. The device has also been optimized
for EMC conditions.
Features
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MARKING
DIAGRAM
8
8
1
SO−8
D1 SUFFIX
CASE 751
1
8
8
1
SO−8
EXPOSED PAD
PD SUFFIX
CASE 751AC
1
14
SO−14
D2 SUFFIX
CASE 751A
1
NCV4269C5G
AWLYWW
4269C5
ALYW
G
4269C5
ALYW
G
14
1
•
•
•
•
•
•
•
•
•
•
•
•
•
5.0 V
±
2.0% Output
Low 125
mA
Quiescent Current
Active Reset Output Low Down to V
Q
= 1.0 V
Adjustable Reset Threshold
150 mA Output Current Capability
Fault Protection
♦
+60 V Peak Transient Voltage
♦
−40 V Reverse Voltage
♦
Short Circuit
♦
Thermal Overload
Early Warning through SI/SO Leads
Internally Fused Leads in SO−14 Package
Integrated Pullup Resistor at Logic Outputs (To Use External
Resistors, Select the NCV4279C)
Very Low Dropout Voltage
Electrical Parameters Guaranteed Over Entire Temperature Range
AEC−Q100 Grade 1 Qualified and PPAP Capable
These are Pb−Free Devices
14
1
TSSOP−14 EP
PA SUFFIX
CASE 948AW
V426
9C50
ALYWG
G
A
WL, L
Y
WW, W
G,
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb Free
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2015
1
June, 2015 − Rev. 3
Publication Order Number:
NCV4269C/D
NCV4269C
I
Reference
and Trim
Q
Current and
Saturation
Control
R
SO
R
RO
Error
Amplifier
D
RO
or
Reference
SO
R
ADJ
SI
+
−
GND
Figure 1. Block Diagram
PIN CONNECTIONS
1
I
SI
R
ADJ
D
1
8
Q
SO
RO
GND
R
ADJ
D
GND
GND
GND
GND
RO
SO−14
14
SI
I
GND
GND
GND
Q
SO
R
ADJ
NC
D
GND
NC
NC
RO
1
14
SI
I
NC
Q
NC
NC
SO
SO−8
TSSOP−14 EP
PACKAGE PIN DESCRIPTION
Package Pin Number
SO−8
3
4
5
−
6
7
8
1
2
−
SO−8 EP
3
4
5
−
6
7
8
1
2
EPAD
SO−14
1
2
3, 4, 5, 6,
10, 11, 12
−
7
8
9
13
14
−
TSSOP14
1
3
4
2, 5, 6, 9,
10, 12
7
8
11
13
14
EPAD
Pin
Symbol
R
ADJ
D
GND
NC
RO
SO
Q
I
SI
EPAD
Function
Reset Threshold Adjust; if not used to connect to GND.
Reset Delay; To Set Time Delay, Connect to GND with Capacitor
Ground
No connection to these pins from the IC.
Reset Output; The Open−Collector Output has a 20 kW Pullup Resistor to
Q. Leave Open if Not Used.
Sense Output; This Open−Collector Output is Internally Pulled Up by 20 kW
pullup resistor to Q. If not used, keep open.
5 V Output; Connect to GND with a 10
mF
Capacitor, ESR < 2.5
W.
Input; Connect to GND Directly at the IC with Ceramic Capacitor.
Sense Input; If not used, Connect to Q.
Connect to ground potential or leave unconnected
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NCV4269C
MAXIMUM RATINGS
(T
J
= −40°C to 150°C)
Parameter
Input to Regulator
Input Transient to Regulator (Note 3)
Sense Input
Reset Threshold Adjust
Reset Delay
Ground
Reset Output
Sense Output
Regulated Output
Junction Temperature
Storage Temperature
Input Voltage Operating Range
Junction Temperature Operating Range
LEAD TEMPERATURE SOLDERING AND MSL
Parameter
MSL, 8−Lead, 14−Lead, LS Temperature 265°C Peak (Note 4)
MSL, 8−Lead EP, LS Temperature 260°C
Symbol
MSL
MSL
Value
1
2
Symbol
V
I
I
I
V
I
V
SI
I
SI
V
RADJ
I
RADJ
V
D
I
D
I
q
V
RO
I
RO
V
SO
I
SO
V
Q
I
Q
T
J
T
STG
V
I
T
J
Min
−40
Internally Limited
−
−40
−1
−0.3
−10
−0.3
Internally Limited
50
−0.3
Internally Limited
−0.3
Internally Limited
−0.5
−10
−
−50
−
−40
Max
45
Internally Limited
60
45
1
7
10
7
Internally Limited
−
7
Internally Limited
7
Internally Limited
7
−
150
150
45
150
Unit
V
V
V
mA
V
mA
V
mA
V
V
V
mA
°C
°C
V
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. This device series incorporates ESD protection and exceeds the following ratings:
Human Body Model (HBM)
≤
4.0 kV per AEC−Q100−002.
Machine Model (MM)
≤
200 V per AEC−Q100−003.
2. Latchup tested per AEC−Q100−004.
3. Load Dump Test B (with centralized load dump suppression) according to ISO16750−2 standard. Guaranteed by design. Not tested in
production. Passed Class A according to ISO16750−1.
4. +5°C/−0°C, 40 Sec Max−at−Peak, 60 − 150 Sec above 217°C.
THERMAL CHARACTERISTICS
Characteristic
SO−8 Package (Note 5)
Junction−to−Pin 6 (Y − JL6,
Y
L6
)
Junction−to−Ambient Thermal Resistance (R
qJA
,
q
JA
)
SO−8 EP Package (Note 5)
Junction−to−Pin 8 (Y − JL8,
Y
L8
)
Junction−to−Ambient Thermal Resistance (R
qJA
,
q
JA
)
Junction−to−Pad (Y − JPad)
SO−14 Package (Note 5)
Junction−to−Pin 4 (Y − JL4,
Y
L4
)
Junction−to−Ambient Thermal Resistance (R
qJA
,
q
JA
)
TSSOP−14 EP Package (Note 5)
Junction−to−Pin 3 (Y − JL3,
Y
L3
)
Junction−to−Ambient Thermal Resistance (R
qJA
,
q
JA
)
Junction−to−Pad (Y − JPad)
5. 2 oz copper, 150 mm
2
copper area, 1.5 mm thick FR4
19.3
77.3
12.6
°C/W
°C/W
°C/W
19.5
100.9
°C/W
°C/W
47
131.6
16.3
°C/W
°C/W
°C/W
58.3
151.1
°C/W
°C/W
Test Conditions (Typical Values)
Unit
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NCV4269C
ELECTRICAL CHARACTERISTICS
(T
J
= −40°C
≤
T
J
≤
150°C, V
I
= 13.5 V unless otherwise specified)
Characteristic
REGULATOR
Output Voltage
Current Limit
Current Consumption; I
q
= I
I
– I
Q
Current Consumption; I
q
= I
I
– I
Q
Current Consumption; I
q
= I
I
– I
Q
Dropout Voltage
Load Regulation
Line Regulation
RESET GENERATOR
Reset Switching Threshold
Reset Adjust Switching Threshold
Reset Pullup Resistance
Reset Output Saturation Voltage
Upper Delay Switching Threshold
Lower Delay Switching Threshold
Saturation Voltage on Delay Capacitor
Charge Current
Delay Time L
³
H
Delay Time H
³
L
INPUT VOLTAGE SENSE
Sense Threshold High
Sense Threshold Low
Sense Output Saturation Voltage
Sense Resistor Pullup
Sense Input Current
THERMAL SHUTDOWN
Thermal Shutdown Temperature (Note 6)
T
SD
Iout = 1 mA
150
−
200
°C
V
SI,High
V
SI,Low
V
SO,Low
R
SO,INT
I
SI
−
−
V
SI
< 1.20 V; V
Q
> 3 V; R
SO,INT
−
−
1.24
1.16
−
10
−1.0
1.31
1.20
0.03
20
0.1
1.38
1.28
0.4
40
1.0
V
V
V
kW
mA
V
RT
V
RADJ,TH
R
RO,INT
V
RO,SAT
V
UD
V
LD
V
D,SAT
I
D,C
t
d
t
RR
−
V
Q
> 3.5 V
−
V
Q
< V
RT
, R
RO, INT
−
−
V
Q
< V
RT
V
D
= 1 V
C
D
= 100 nF
C
D
= 100 nF
4.50
1.26
10
−
1.4
0.3
−
3.0
17
−
4.65
1.35
20
0.03
1.8
0.45
−
6.5
28
1.5
4.80
1.44
40
0.4
2.2
0.60
0.1
9.5
73
−
V
V
kW
V
V
V
V
mA
ms
ms
V
Q
I
Q
I
q
I
q
I
q
V
dr
DV
Q
DV
Q
1 mA
v
I
Q
v
100 mA 6 V
v
V
I
v
16 V
−
I
Q
= 1 mA, RO, SO High
I
Q
= 10 mA, RO, SO High
I
Q
= 50 mA, RO, SO High
V
I
= 5 V, I
Q
= 100 mA
I
Q
= 5 mA to 100 mA
V
I
= 6 V to 26 V I
Q
= 1 mA
4.90
150
−
−
−
−
−
−
5.00
430
125
230
0.9
0.23
1
1
5.10
500
250
450
3.0
0.5
20
30
V
mA
mA
mA
mA
V
mV
mV
Symbol
Test Conditions
Min
Typ
Max
Unit
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
6. Values based on design and/or characterization.
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4
NCV4269C
I
I
I
Q
I
C
I
470 nF
I
SI
SI
D
Q
1000
mF
R
ADJ1
I
RADJ
C
Q
22
mF
V
Q
V
I
GND
RO
RADJ
SO
V
SI
I
D
I
q
V
RO
V
SO
V
RADJ
C
D
100 nF
V
D
R
ADJ2
Figure 2. Measuring Circuit
V
I
t
V
Q
V
RT
t
V
D
V
UD
V
LD
t
t
d
V
RO
V
RO,SAT
t
RR
dV
I
+
D
dt
CD
< t
RR
t
Thermal
Shutdown
Voltage Dip
at Input
Undervoltage
Secondary
Spike
Overload
at Output
Power−on−Reset
Figure 3. Reset Timing Diagram
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