L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
DESCRIPTION
The
L4C381
is a flexible, high speed,
cascadable 16-bit Arithmetic and
Logic Unit. It combines four 381-type
4-bit ALUs, a look-ahead carry
generator, and miscellaneous interface
logic — all in a single 68-pin package.
While containing new features to
support high speed pipelined architec-
tures and single 16-bit bus configura-
tions, the L4C381 retains full perform-
ance and functional compatibility with
the bipolar ’381 designs.
The L4C381 can be cascaded to
perform 32-bit or greater operations.
See “Cascading the L4C381” toward
the end of this data sheet for more
information.
ARCHITECTURE
The L4C381 operates on two 16-bit
operands (A and B) and produces a
16-bit result (F). Three select lines
control the ALU and provide 3
arithmetic, 3 logical, and 2 initializa-
tion functions. Full ALU status is
provided to support cascading to
longer word lengths. Registers are
provided on both the ALU inputs and
the output, but these may be bypassed
under user control. An internal
feedback path allows the registered
ALU output to be routed to one of the
ALU inputs, accommodating chain
operations and accumulation. Fur-
thermore, the A or B input can be
forced to Zero allowing unary func-
tions on either operand.
ALU OPERATIONS
FTAB
FEATURES
u
High-Speed (15ns), Low Power
16-bit Cascadable ALU
u
Implements Add, Subtract, Accumu-
late, Two’s Complement, Pass, and
Logic Operations
u
All Registers Have a Bypass Path
for Complete Flexibility
u
68-pin PLCC, J-Lead
L4C381 B
LOCK
D
IAGRAM
A
15
-A
0
16
B
15
-B
0
16
ENA
A REGISTER
B REGISTER
ENB
0
0
2
The S
2
–S
0
lines specify the operation
to be performed. The ALU functions
and their select codes are shown in
Table 1.
The two functions, B minus A and
A minus B, can be achieved by setting
the carry input of the least significant
slice and selecting codes 001 and 010
respectively.
OSA
OSB
P, G, C
16
OVF, Z
5
4
ALU
16
S
2
-S
0
, C
0
T
ABLE
1.
RESULT REGISTER
ENF
A
LU
F
UNCTIONS
FUNCTION
CLEAR (F = 00
• • •
00)
NOT(A) + B
A + NOT(B)
A+B
A XOR B
A OR B
A AND B
PRESET (F = 11
• • •
11)
S
2
-S
0
000
001
FTF
16
OE
16
010
011
100
101
110
111
CLK
TO ALL REGISTERS
F
15
-F
0
Arithmetic Logic Units
1
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
T
ABLE
2.
ALU S
TATUS
F
LAGS
fri=0..1
o
. 5
fri=0..1
o
. 5
ALU STATUS
The ALU provides Overflow and Zero
status bits. Carry, Propagate, and
Generate outputs are also provided
for cascading. These outputs are
defined for the three arithmetic
functions only. The ALU sets the Zero
output when all 16 output bits are
zero. The Generate, Propagate, C
16
,
and OVF flags for the A + B operation
are defined in Table 2. The status
flags produced for NOT(A) + B and
A + NOT(B) can be found by comple-
menting A
i
and B
i
respectively in
Table 2.
OPERAND REGISTERS
The L4C381 has two 16-bit wide in-
put registers for operands A and B.
These registers are rising edge trig-
gered by a common clock. The A
register is enabled for input by setting
the ENA control LOW, and the B
register is enabled for input by setting
the ENB control LOW. When either
the ENA control or ENB control is
HIGH, the data in the corresponding
input register will not change.
This architecture allows the L4C381 to
accept arguments from a single 16-bit
data bus. For those applications that
do not require registered inputs, both
the A and B operand registers can be
bypassed with the FTAB control line.
When the FTAB control is asserted
(FTAB = HIGH), data is routed
around the A and B input registers;
however, they continue to function
normally via the ENA and ENB
controls. The contents of the input
registers will again be available to the
ALU if the FTAB control is released.
OUTPUT REGISTER
The output of the ALU drives the
input of a 16-bit register. This rising-
edge-triggered register is clocked by
the same clock as the input registers.
When the ENF control is LOW, data
from the ALU will be clocked into the
Bit Carry Generate = g
i
= A
i i
B
Bit Carry Propagate = p
i
= A
i
+ B
i
P
0
= p
0
P
i
= p
i
(
i–1
)
P
and
G
0
= g
0
G
i
= g
i
+ p
i
(G
i–1
)
C
i
= G
i–1
+ P
i–1
(
0
)
C
then
G
P
C
16
OVF
=
=
=
=
NOT(G
15
)
NOT(P
15
)
G
15
+ P
15
C
0
C
15
XOR C
16
fri=1..1
o
. 5
fri=1..1
o
. 5
fri=1..1
o
. 5
output register. By disabling the
output register, intermediate results
can be held while loading new input
operands. Three-state drivers con-
trolled by the OE input allow the
L4C381 to be configured in a single
bidirectional bus system.
The output register can be bypassed
by asserting the FTF control signal
(FTF = HIGH). When the FTF control
is asserted, output data is routed
around the output register, however,
it continues to function normally via
the ENF control. The contents of the
output register will again be available
on the output pins if FTF is released.
With both FTAB and FTF true (HIGH)
the L4C381 is functionally identical to
four cascaded 54S381-type devices.
OPERAND SELECTION
The two operand select lines, OSA and
OSB, control multiplexers that precede
the ALU inputs. These multiplexers
provide an operand force-to-zero
function as well as F register feedback
to the B input. Table 3 shows the
inputs to the ALU as a function of the
operand select inputs. Either the A or
B operands may be forced to zero.
T
ABLE
3. O
PERAND
S
ELECTION
OSB
OSA
OPERAND B
OPERAND A
0
0
1
1
0
1
0
1
F
0
B
B
A
A
0
A
When both operand select lines are
low, the L4C381 is configured as a
chain calculation ALU. The registered
ALU output is passed back to the B
input to the ALU. This allows accu-
mulation operations to be performed
by providing new operands via the A
input port. The accumulator can be
preloaded from the A input by setting
OSA true. By forcing the function
select lines to the CLEAR state (000),
the accumulator may be cleared. Note
that this feedback operation is not
affected by the state of the FTF
control. That is, the F outputs of the
L4C381 may be driven directly by the
ALU. The output register continues to
function, however, and provides the
ALU B operand source.
Arithmetic Logic Units
2
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
M
AXIMUM
R
ATINGS
Above which useful life may be impaired (Notes 1, 2, 3, 8)
Storage temperature ........................................................................................................... –65°C to +150°C
Operating ambient temperature ........................................................................................... –55°C to +125°C
V
CC
supply voltage with respect to ground ............................................................................ –0.5 V to +7.0 V
Input signal with respect to ground ........................................................................................ –3.0 V to +7.0 V
Signal applied to high impedance output ............................................................................... –3.0 V to +7.0 V
Output current into low outputs ............................................................................................................. 25 mA
Latchup current ............................................................................................................................... > 400 mA
O
PERATING
C
ONDITIONS
To meet specified electrical and switching characteristics
Mode
Active Operation, Commercial
Active Operation, Military
Temperature Range
(Ambient)
0°C to +70°C
–55°C to +125°C
Supply
Voltage
4.75 V
≤
V
CC
≤
5.25 V
4.50 V
≤
V
CC
≤
5.50 V
E
LECTRICAL
C
HARACTERISTICS
Over Operating Conditions (Note 4)
Symbol
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
CC1
I
CC2
Parameter
Output High Voltage
Output Low Voltage
Input High Voltage
Input Low Voltage
Input Current
Output Leakage Current
V
CC
Current, Dynamic
V
CC
Current, Quiescent
(Note 3)
Test Condition
V
CC
= Min.,
I
OH
= –2.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
Min
2.4
Typ
Max
Unit
V
0.5
2.0
0.0
V
CC
0.8
±20
±20
15
30
1.5
V
V
V
µA
µA
mA
mA
Ground
≤
V
IN
≤
V
CC
(Note 12)
Ground
≤
V
OUT
≤
V
CC
(Note 12)
(Notes 5, 6)
(Note 7)
Arithmetic Logic Units
3
08/16/2000–LDS.381-P
432109876543210987654321
432109876543210987654321
432109876543210987654321
*D
ISCONTINUED
S
PEED
G
RADE
t
DIS
t
ENA
ENA, ENB, ENF
S
2
-S
0
, OSA, OSB
C
0
A
15
-A
0
, B
15
-B
0
Input
FTAB = 1, FTF = 1
A
15
-A
0
, B
15
-B
0
Clock (OSA, OSB = 0)
C
0
S
2
-S
0
, OSA, OSB
FTAB = 1, FTF = 0
A
15
-A
0
, B
15
-B
0
Clock
C
0
S
2
-S
0
, OSA, OSB
FTAB = 0, FTF = 1
Clock
C
0
S
2
-S
0
, OSA, OSB
FTAB = 0, FTF = 0
Clock
From Input
C
0
S
2
-S
0
, OSA, OSB
L4C381-55*
To Output
20
20
18
16
Lowgoing Pulse
Highgoing Pulse
DEVICES INCORPORATED
G
UARANTEED
M
AXIMUM
C
OMBINATIONAL
D
ELAYS
Notes 9, 10 (ns)
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
F
15
-F
0
55
56
37
55
—
32
—
—
56
37
55
32
—
—
L4C381-55*
P, G OVF, Z
36
38
—
42
38
—
42
38
—
36
—
—
42
42
46
53
34
42
46
—
34
42
53
34
42
53
34
42
C
16
F
15
-F
0
37
36
22
42
37
—
22
42
36
22
42
36
22
42
40
46
30
40
—
26
—
—
46
30
40
26
—
—
L4C381-40*
P, G OVF, Z
30
30
—
32
30
—
—
32
30
—
32
32
30
—
40
44
28
34
40
—
28
34
44
28
34
34
44
28
C
16
F
15
-F
0
32
32
20
35
32
—
20
35
32
20
35
35
32
20
26
28
22
26
—
22
—
—
28
22
26
22
—
—
L4C381-26*
P, G OVF, Z
22
22
—
22
22
—
—
22
22
—
22
22
22
—
22
—
18
22
22
22
26
18
22
26
18
22
26
18
C
16
22
—
18
22
22
22
22
18
22
22
18
22
22
18
G
UARANTEED
M
INIMUM
S
ETUP AND
H
OLD
T
IMES
W
ITH
R
ESPECT TO
C
LOCK
R
ISING
E
DGE
Notes 9, 10 (ns)
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
432109876543212109876543210987654321098765432121098765432109876543210987654321
Setup Hold
FTAB = 0
10
44
21
8
L4C381-55*
2
0
0
2
Setup Hold
FTAB = 1
10
44
21
35
2
0
0
2
Setup Hold
FTAB = 0
10
32
16
8
L4C381-40*
2
2
0
0
Setup Hold Setup Hold
FTAB = 1
28
10
32
16
2
2
0
0
FTAB = 0
18
8
8
8
L4C381-26*
2
0
0
2
Setup Hold
FTAB = 1
18
16
8
8
2
0
0
2
T
RI
-S
TATE
E
NABLE
/D
ISABLE
T
IMES
Notes 9, 10, 11 (ns)
SWITCHING CHARACTERISTICS — C
OMMERCIAL
O
PERATING
R
ANGE
(0°C to +70°C)
C
LOCK
C
YCLE
T
IME AND
P
ULSE
W
IDTH
Notes 9, 10 (ns)
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
L4C381-55*
15
15
43
L4C381-40*
10
10
34
L4C381-26*
10
10
20
65432121098765432109876543210987654321
65432121098765432109876543210987654321
6543212109876543210987654321098765432
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
65432121098765432109876543210987654321
5432121098765432109876543210987654321
65432121098765432109876543210987654321
6
1
L4C381-40*
18
L4C381-26*
16
Minimum Cycle Time
4
16-bit Cascadable ALU
Arithmetic Logic Units
L4C381
08/16/2000–LDS.381-P
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
SWITCHING CHARACTERISTICS — C
OMMERCIAL
O
PERATING
R
ANGE
(0°C to +70°C)
G
UARANTEED
M
AXIMUM
C
OMBINATIONAL
D
ELAYS
Notes 9, 10 (ns)
To Output
From Input
FTAB = 0, FTF = 0
Clock
C
0
S
2
-S
0
, OSA, OSB
FTAB = 0, FTF = 1
Clock
C
0
S
2
-S
0
, OSA, OSB
FTAB = 1, FTF = 0
A
15
-A
0
, B
15
-B
0
Clock
C
0
S
2
-S
0
, OSA, OSB
FTAB = 1, FTF = 1
A
15
-A
0
, B
15
-B
0
Clock (OSA, OSB = 0)
C
0
S
2
-S
0
, OSA, OSB
20
18
20
20
—
18
20
14
20
20
14
18
15
14
15
15
—
14
15
13
15
15
13
14
F
15
-F
0
L4C381-20
P, G OVF, Z
C
16
F
15
-F
0
L4C381-15
P, G OVF, Z
C
16
11
—
—
20
—
18
20
14
20
20
14
18
11
—
—
15
—
14
15
13
15
15
13
14
—
11
—
—
16
—
—
18
20
—
14
20
17
—
14
18
—
11
—
—
14
—
—
14
15
—
13
15
14
—
13
14
20
20
18
20
16
20
—
18
20
20
14
20
17
20
14
18
15
15
14
15
14
15
—
14
15
15
13
15
14
15
13
14
G
UARANTEED
M
INIMUM
S
ETUP AND
H
OLD
T
IMES
W
ITH
R
ESPECT TO
C
LOCK
R
ISING
E
DGE
Notes 9, 10 (ns)
L4C381-20
FTAB = 0
Input
A
15
-A
0
, B
15
-B
0
C
0
S
2
-S
0
, OSA, OSB
ENA, ENB, ENF
Setup Hold
5
12
15
5
0
0
0
0
FTAB = 1
Setup Hold
14
12
15
5
0
0
0
0
L4C381-15
FTAB = 0
Setup Hold
5
10
12
5
0
0
0
0
FTAB = 1
Setup Hold
12
10
12
5
0
0
0
0
T
RI
-S
TATE
E
NABLE
/D
ISABLE
T
IMES
Notes 9, 10, 11 (ns)
L4C381-20
t
ENA
t
DIS
8
8
L4C381-15
6
6
C
LOCK
C
YCLE
T
IME AND
P
ULSE
W
IDTH
Notes 9, 10 (ns)
L4C381-20
Minimum Cycle Time
L4C381-15
14
4
4
18
5
5
Highgoing Pulse
Lowgoing Pulse
Arithmetic Logic Units
5
08/16/2000–LDS.381-P
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