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L4C381JC15

Description
16-bit Cascadable ALU
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size107KB,12 Pages
ManufacturerLOGIC Devices
Websitehttp://www.logicdevices.com/
Download Datasheet Parametric Compare View All

L4C381JC15 Overview

16-bit Cascadable ALU

L4C381JC15 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerLOGIC Devices
Parts packaging codeLCC
package instructionQCCJ,
Contacts68
Reach Compliance Codecompli
ECCN code3A001.A.3
Other features2 X 16 BIT INPUT BUS
maximum clock frequency66.67 MHz
External data bus width16
JESD-30 codeS-PQCC-J68
JESD-609 codee0
length24.2316 mm
Humidity sensitivity level3
Number of terminals68
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum slew rate30 mA
Maximum supply voltage5.25 V
Minimum supply voltage4.75 V
Nominal supply voltage5 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width24.2316 mm
uPs/uCs/peripheral integrated circuit typeBIT-SLICE MICROPROCESSOR
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
L4C381
DEVICES INCORPORATED
16-bit Cascadable ALU
DESCRIPTION
The
L4C381
is a flexible, high speed,
cascadable 16-bit Arithmetic and
Logic Unit. It combines four 381-type
4-bit ALUs, a look-ahead carry
generator, and miscellaneous interface
logic — all in a single 68-pin package.
While containing new features to
support high speed pipelined architec-
tures and single 16-bit bus configura-
tions, the L4C381 retains full perform-
ance and functional compatibility with
the bipolar ’381 designs.
The L4C381 can be cascaded to
perform 32-bit or greater operations.
See “Cascading the L4C381” toward
the end of this data sheet for more
information.
ARCHITECTURE
The L4C381 operates on two 16-bit
operands (A and B) and produces a
16-bit result (F). Three select lines
control the ALU and provide 3
arithmetic, 3 logical, and 2 initializa-
tion functions. Full ALU status is
provided to support cascading to
longer word lengths. Registers are
provided on both the ALU inputs and
the output, but these may be bypassed
under user control. An internal
feedback path allows the registered
ALU output to be routed to one of the
ALU inputs, accommodating chain
operations and accumulation. Fur-
thermore, the A or B input can be
forced to Zero allowing unary func-
tions on either operand.
ALU OPERATIONS
FTAB
FEATURES
u
High-Speed (15ns), Low Power
16-bit Cascadable ALU
u
Implements Add, Subtract, Accumu-
late, Two’s Complement, Pass, and
Logic Operations
u
All Registers Have a Bypass Path
for Complete Flexibility
u
68-pin PLCC, J-Lead
L4C381 B
LOCK
D
IAGRAM
A
15
-A
0
16
B
15
-B
0
16
ENA
A REGISTER
B REGISTER
ENB
0
0
2
The S
2
–S
0
lines specify the operation
to be performed. The ALU functions
and their select codes are shown in
Table 1.
The two functions, B minus A and
A minus B, can be achieved by setting
the carry input of the least significant
slice and selecting codes 001 and 010
respectively.
OSA
OSB
P, G, C
16
OVF, Z
5
4
ALU
16
S
2
-S
0
, C
0
T
ABLE
1.
RESULT REGISTER
ENF
A
LU
F
UNCTIONS
FUNCTION
CLEAR (F = 00
• • •
00)
NOT(A) + B
A + NOT(B)
A+B
A XOR B
A OR B
A AND B
PRESET (F = 11
• • •
11)
S
2
-S
0
000
001
FTF
16
OE
16
010
011
100
101
110
111
CLK
TO ALL REGISTERS
F
15
-F
0
Arithmetic Logic Units
1
08/16/2000–LDS.381-P

L4C381JC15 Related Products

L4C381JC15 L4C381JC20 L4C381
Description 16-bit Cascadable ALU 16-bit Cascadable ALU 16-bit Cascadable ALU
Is it lead-free? Contains lead Contains lead -
Is it Rohs certified? incompatible incompatible -
Maker LOGIC Devices LOGIC Devices -
Parts packaging code LCC LCC -
package instruction QCCJ, QCCJ, -
Contacts 68 68 -
Reach Compliance Code compli compli -
ECCN code 3A001.A.3 3A001.A.3 -
Other features 2 X 16 BIT INPUT BUS 2 X 16 BIT INPUT BUS -
maximum clock frequency 66.67 MHz 50 MHz -
External data bus width 16 16 -
JESD-30 code S-PQCC-J68 S-PQCC-J68 -
JESD-609 code e0 e0 -
length 24.2316 mm 24.2316 mm -
Humidity sensitivity level 3 3 -
Number of terminals 68 68 -
Maximum operating temperature 70 °C 70 °C -
Package body material PLASTIC/EPOXY PLASTIC/EPOXY -
encapsulated code QCCJ QCCJ -
Package shape SQUARE SQUARE -
Package form CHIP CARRIER CHIP CARRIER -
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED -
Certification status Not Qualified Not Qualified -
Maximum seat height 5.08 mm 5.08 mm -
Maximum slew rate 30 mA 30 mA -
Maximum supply voltage 5.25 V 5.25 V -
Minimum supply voltage 4.75 V 4.75 V -
Nominal supply voltage 5 V 5 V -
surface mount YES YES -
technology CMOS CMOS -
Temperature level COMMERCIAL COMMERCIAL -
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) -
Terminal form J BEND J BEND -
Terminal pitch 1.27 mm 1.27 mm -
Terminal location QUAD QUAD -
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED -
width 24.2316 mm 24.2316 mm -
uPs/uCs/peripheral integrated circuit type BIT-SLICE MICROPROCESSOR BIT-SLICE MICROPROCESSOR -
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