DRAM MODULE
KMM53232004CK/CKG EDO Mode
32M x 32 DRAM SIMM Using 16Mx4, 4K Refresh, 5V
GENERAL DESCRIPTION
The Samsung KMM53232004C is a 32Mx32bits Dynamic
RAM high density memory module. The Samsung
KMM53232004C consists of sixteen CMOS 16Mx4bits
DRAMs in SOJ packages mounted on a 72-pin glass-epoxy
substrate. A 0.1 or 0.22uF decoupling capacitor is mounted
on the printed circuit board for each DRAM. The
KMM53232004C is a Single In-line Memory Module with edge
connections and is intended for mounting into 72 pin edge
connector sockets.
KMM53232004CK/CKG
FEATURES
• Part Identification
- KMM53232004CK(4K cycles/64ms Ref, SOJ, Solder)
- KMM53232004CKG(4K cycles/64ms Ref, SOJ, Gold)
• Extended Data Out Mode Operation
• CAS-before-RAS & Hidden Refresh capability
• RAS-only refresh capability
• TTL compatible inputs and outputs
• Single +5V±10% power supply
• JEDEC standard PDpin & pinout
• PCB : Height(1420mil), double sided component
PERFORMANCE RANGE
Speed
-5
-6
t
RAC
50ns
60ns
t
CAC
13ns
15ns
t
RC
84ns
104ns
t
HPC
20ns
25ns
PIN CONFIGURATIONS
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Symbol
V
SS
DQ0
DQ18
DQ1
DQ19
DQ2
DQ20
DQ3
DQ21
Vcc
NC
A0
A1
A2
A3
A4
A5
A6
A10
DQ4
DQ22
DQ5
DQ23
DQ6
DQ24
DQ7
DQ25
A7
A11
Vcc
A8
A9
RAS3
RAS2
NC
NC
Pin
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
Symbol
NC
NC
Vss
CAS0
CAS2
CAS3
CAS1
RAS0
RAS1
NC
W
NC
DQ9
DQ27
DQ10
DQ28
DQ11
DQ29
DQ12
DQ30
DQ13
DQ31
Vcc
DQ32
DQ14
DQ33
DQ15
DQ34
DQ16
NC
PD1
PD2
PD3
PD4
NC
Vss
PIN NAMES
Pin Name
A0 - A11
DQ0-7, DQ9-16
DQ18-25, DQ27-34
W
RAS0 - RAS3
CAS0 - CAS3
PD1 -PD4
Vcc
Vss
NC
Function
Address Inputs
Data In/Out
Read/Write Enable
Row Address Strobe
Column Address Strobe
Presence Detect
Power(+5V)
Ground
No Connection
PRESENCE DETECT PINS (Optional)
Pin
PD1
PD2
PD3
PD4
50NS
NC
Vss
Vss
Vss
60NS
NC
Vss
NC
NC
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
DRAM MODULE
ABSOLUTE MAXIMUM RATINGS *
Item
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Output Current
Symbol
V
IN
, V
OUT
V
CC
T
stg
P
d
I
OS
KMM53232004CK/CKG
Rating
-1 to +7.0
-1 to +7.0
-55 to +125
16
50
Unit
V
V
°C
W
mA
* Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage referenced to V
SS
, T
A
= 0 to 70°C)
Item
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Symbol
V
CC
V
SS
V
IH
V
IL
Min
4.5
0
2.4
-1.0
*2
Typ
5.0
0
-
-
Max
5.5
0
V
CC*1
0.8
Unit
V
V
V
V
*1 : V
CC
+2.0V at pulse width≤20ns, which is measured at V
CC
.
*2 : -2.0V at pulse width≤20ns, whcih is measured at V
SS
.
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted)
Symbol
I
CC1
I
CC2
I
CC3
I
CC4
I
CC5
I
CC6
I
I(L)
I
O(L)
V
OH
V
OL
Speed
-5
-6
Don′t care
-5
-6
-5
-6
Don′t care
-5
-6
Don′t care
Don′t care
KMM53232004CK/CKG
Min
-
-
Max
976
896
32
976
896
896
816
16
976
896
10
10
-
0.4
Unit
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
uA
uA
V
V
-
-
-
-
-
-
-
-
-10
-10
2.4
-
I
CC1
: Operating Current * (RAS, CAS, Address cycling @
t
RC
=min)
I
CC2
: Standby Current (RAS=CAS=W=V
IH
)
I
CC3
: RAS Only Refresh Current * (CAS=V
IH
, RAS cycling @
t
RC
=min)
I
CC4
: Hyper Page Mode Current * (RAS=V
IL
, CAS cycling :
t
HPC
=min)
I
CC5
: Standby Current (RAS=CAS=W=Vcc-0.2V)
I
CC6
: CAS-Before-RAS Refresh Current * (RAS and CAS cycling @
t
RC
=min)
I(
IL)
: Input Leakage Current (Any input 0≤V
IN
≤Vcc+0.5V,
all other pins not under test=0 V)
I(
OL)
: Output Leakage Current(Data Out is disabled, 0V≤V
OUT
≤Vcc)
V
OH
: Output High Voltage Level (I
OH
= -5mA)
V
OL
: Output Low Voltage Level (I
OL
= 4.2mA)
* NOTE
: I
CC1
, I
CC3
, I
CC4
and I
CC6
are dependent on output loading and cycle rates. Specified values are obtained with the output open.
I
CC
is specified as an average current. In I
CC1
and I
CC3
, address can be changed maximum once while RAS=V
IL
. In I
CC4
,
address can be changed maximum once within one EDO mode cycle time,
t
HPC
.
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
