Features
•
•
•
•
•
•
•
•
•
Dual ADC with 8-bit Resolution
1 Gsps Sampling Rate per Channel, 2 Gsps in Interlaced Mode
Single or 1:2 Demultiplexed Output
LVDS Output Format (100Ω)
500 mVpp Analog Input (Differential Only)
Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs
Power Supply: 3.3V (Analog), 3.3V (Digital), 2.25V (Output)
LQFP144 Package
Temperature Range:
– 0°C < TA < 70°C (Commercial Grade)
– -40°C < TA < 85°C (Industrial Grade)
•
3-wire Serial Interface
– 16-bit Data, 3-bit Address
– 1:2 or 1:1 Output Demultiplexer Ratio Selection
– Full or Partial Standby Mode
– Analog Gain (±1.5 dB) Digital Control
– Input Clock Selection
– Analog Input Switch Selection
– Binary or Gray Logical Outputs
– Synchronous Data Ready Reset
– Data Ready Delay Adjustable on Both Channels
– Interlacing Functions:
Offset and Gain (Channel to Channel) Calibration
Digital Fine SDA (Fine Sampling Delay Adjust) on One Channel
– Internal Static or Dynamic Built-In Test (BIT)
Dual 8-bit
1 Gsps ADC
AT84AD001B
Smart ADC
™
Performance
•
•
•
•
•
•
•
•
•
Low Power Consumption: 0.7W Per Channel
Power Consumption in Standby Mode: 120 mW
1.5 GHz Full Power Input Bandwidth (-3 dB)
SNR = 42 dB Typ (6.8 ENOB), THD = -51 dBc, SFDR = -54 dBc at Fs = 1 Gsps
Fin = 500 MHz
2-tone IMD3: -54 dBc (499 MHz, 501 MHz) at 1 Gsps
DNL = 0.25 LSB, INL = 0.5 LSB
Channel to Channel Input Offset Error: 0.5 LSB Max (After Calibration)
Gain Matching (Channel to Channel): 0.5 LSB Max (After Calibration)
Low Bit Error Rate (10
-13
) at 1 Gsps
Application
•
•
•
•
Instrumentation
Satellite Receivers
Direct RF Down Conversion
WLAN
2153C–BDC–04/04
1
Description
The AT84AD001B is a monolithic dual 8-bit analog-to-digital converter, offering low
1.4W power consumption and excellent digitizing accuracy. It integrates dual on-chip
track/holds that provide an enhanced dynamic performance with a sampling rate of up to
1 Gsps and an input frequency bandwidth of over 1.5 GHz. The dual concept, the inte-
grated demultiplexer and the easy interleaving mode make this device user-friendly for
all dual channel applications, such as direct RF conversion or data acquisition. The
smart
function of the 3-wire serial interface eliminates the need for external compo-
nents, which are usually necessary for gain and offset tuning and setting of other
parameters, leading to space and power reduction as well as system flexibility.
Functional Description
The AT84AD001B is a dual 8-bit 1 Gsps ADC based on advanced high-speed
BiCMOS technology.
Each ADC includes a front-end analog multiplexer followed by a Sample and Hold (S/H),
and an 8-bit flash-like architecture core analog-to-digital converter. The output data is
followed by a switchable 1:1 or 1:2 demultiplexer and LVDS output buffers (100Ω).
Two over-range bits are provided for adjustment of the external gain control on each
channel.
A 3-wire serial interface (3-bit address and 16-bit data) is included to provide several
adjustments:
•
•
•
•
•
Analog input range adjustment (±1.5 dB) with 8-bit data control using a 3-wire bus
interface (steps of 0.18 dB)
Analog input switch: both ADCs can convert the same analog input signal I or Q
Gray or binary encoder output. Output format: DMUX 1:1 or 1:2 with control of the
output frequency on the data ready output signal
Partial or full standby on channel I or channel Q
Clock selection:
–
–
–
•
•
•
•
Two independent clocks: CLKI and CLKQ
One master clock (CLKI) with the same phase for channel I and channel Q
One master clock but with two phases (CLKI for channel I and CLKIB for
channel Q)
ISA: Internal Settling Adjustment on channel I and channel Q
FiSDA: Fine Sampling Delay Adjustment on channel Q
Adjustable Data Ready Output Delay on both channels
Test mode: decimation mode (by 16), Built-In Test.
A calibration phase is provided to set the two DC offsets of channel I and channel Q
close to code 127.5 and calibrate the two gains to achieve a maximum difference of
0.5 LSB. The offset and gain error can also be set externally via the 3-wire serial
interface.
The AD84AD001B operates in fully differential mode from the analog inputs up to the
digital outputs. The AD84AD001B features a full-power input bandwidth of 1.5 GHz.
2
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 1.
Simplified Block Diagram
CLKI
Clock Buffer
DDRB
Divider
2 to16
DRDA
I
LVDS
Clock
Buffer
2
CLKIO
16
DoirI
Vini
Vinib
-
Gain control I
Calibration
Gain/offset
ISA I
BIT
Input switch
INPUT
MUX
Gain control Q
Calibration
Gain/offset
ISA Q & FiSDA
DoirQ
Vinq
Vinqb
-
+
S/H
8bit
ADC
Q
DMUX
1: 2
or
1: 1
Q
LVDS
buffe r
Q
3-wire Serial Interface
3WSI
DMUX control
2
+
S/H
8bit
ADC
I
DMUX
1:2
or
1:1
I
LVDS
Buffer
I
DOAI
DOAIN
DOBI
DOBIN
DOIRI
DOIRIN
16
2
8
DMUX control
Data
Clock
Ldn
Mode
DOIRQ
DOIRQN
DOAQ
DOAQN
DOBQ
DOBQN
16
16
8
CLKQ
Clock Buffer
DDRB
Divider
2 to 16
DRDA
Q
LVDS
Clock
Buffer
2
CLKQO
3
2153C–BDC–04/04
Typical Applications
Figure 2.
Satellite Receiver Application
Satellite
Low Noise Converter
(Connected to the Dish)
Bandpass
Amplifier
Bandpass
Amplifier
Low Pass
Filter
Satellite Tuner
Tunable
Band Filter
IF
Band Filter
Dish
11..12 GHz
1..2 GHz
Synthesizer
1.5 … 2.5 GHz
AGC
Local oscillator
I
Control Functions:
Clock and Carrier
Recovery...
Q
I
AT84AD001B
I
Local Oscillator
0
Q
90
Q
Clock
Q
Quadrature
Demodulation
4
AT84AD001B
2153C–BDC–04/04
AT84AD001B
Figure 3.
Dual Channel Digital Oscilloscope Application
Channel B
Analog switch
A
DAC
Gain
ADC B
DAC
Offset
DAC
Offset
FISO
RAM
ADC A
Display
µ
P
Channel A
A
DAC
Gain
Channel Mode
Selection
Clock
selection
Timing
circuit
DACs
Smart dual
ADC
DACs
Table 1.
Absolute Maximum Ratings
Parameter
Analog positive supply voltage
Digital positive supply voltage
Output supply voltage
Maximum difference between V
CCA
and V
CCD
Minimum V
CCO
Analog input voltage
Digital input voltage
Clock input voltage
Maximum difference between V
CLK
and V
CLKB
Maximum junction temperature
Storage temperature
Lead temperature (soldering 10s)
Note:
Symbol
V
CCA
V
CCD
V
CCO
V
CCA
to V
CCD
V
CCO
V
INI
or V
INIB
V
INQ
or V
INQB
V
D
V
CLK
or VC
LKB
V
CLK
- V
CLKB
T
J
T
stg
T
leads
Value
3.6
3.6
3.6
± 0.8
1.6
1/-1
-0.3 to V
CCD
+ 0.3
-0.3 to V
CCD
+ 0.3
-2 to 2
125
-65 to 150
300
Unit
V
V
V
V
V
V
V
V
V
°
C
°
C
°
C
Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are
within specified operating conditions. Long exposure to maximum ratings may affect device reliability.
5
2153C–BDC–04/04
Embedded System
京公网安备 11010802033920号
EEWORLD
