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BH62UV8000AI

Description
Ultra Low Power/High Speed CMOS SRAM
File Size125KB,9 Pages
ManufacturerBSI
Websitehttp://www.brilliancesemi.com/
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BH62UV8000AI Overview

Ultra Low Power/High Speed CMOS SRAM

BSI
n
FEATURES
Ultra Low Power/High Speed CMOS SRAM
1M X 8 bit
n
DESCRIPTION
BH62UV8000
Ÿ
Wide V
CC
low operation voltage : 1.65V ~ 3.6V
Ÿ
Ultra low power consumption :
V
CC
= 3.0V
Operation current : 5.0mA at 70ns at 25
O
C
1.5mA at 1MHz at 25
O
C
Standby current : 2.5uA at 25
O
C
V
CC
= 2.0V
Data retention current : 2.5uA at 25
O
C
Ÿ
High speed access time :
-70
70ns at 1.8V at 85
O
C
Ÿ
Automatic power down when chip is deselected
Ÿ
Easy expansion with CE1, CE2 and OE options
Ÿ
Three state outputs and TTL compatible
Ÿ
Fully static operation, no clock, no refreash
Ÿ
Data retention supply voltage as low as 1.0V
The BH62UV8000 is a high performance, ultra low power CMOS Static
Random Access Memory organized as 1,048,576 by 8 bits and
operates in a wide range of 1.65V to 3.6V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with typical operating current of 1.5mA at
1MHz at 3.6V/25
O
C and maximum access time of 70ns at 1.8V/85
O
C.
Easy memory expansion is provided by an active LOW chip enable
(CE1), an active HIGH chip enable (CE2) and active LOW output
enable (OE) and three-state output drivers.
The BH62UV8000 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BH62UV8000 is available in DICE form and 48-ball BGA package.
n
PRODUCT FAMILY
PRODUCT
FAMILY
OPERATING
TEMPERATURE
V
CC
RANGE
SPEED
(ns)
V
CC
=1.8~3.6V
POWER CONSUMPTION
STANDBY
(I
CCSB1
, Max)
Operating
(I
CC
, Max)
PKG TYPE
V
CC
=3.6V V
CC
=1.8V V
CC
=3.6V V
CC
=1.8V
+0
O
C to +70
O
C
BH62UV8000AI
1.65V ~ 3.6V
BH62UV8000DI
-25
O
C to +85
O
C
70
13uA
10uA
10mA
7mA
BGA-48-0608
DICE
70
15uA
12uA
10mA
7mA
n
PIN CONFIGURATIONS
1
A
NC
2
OE
3
A0
4
A1
5
A2
6
CE2
n
BLOCK DIAGRAM
B
NC
NC
A3
A4
CE1
NC
C
DQ0
NC
A5
A6
NC
D04
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
Address
Input
Buffer
10
Row
Decoder
1024
Memory Array
1024 x 18192
D
VSS
DQ1
A17
A7
DQ5
VCC
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
8
8192
Column I/O
Write Driver
Sense Amp
1024
Column Decoder
10
Control
Address Input Buffer
E
VCC
DQ2
VSS
A16
DQ6
VSS
8
F
D3
NC
A14
A15
NC
DQ7
Data
Output
Buffer
G
NC
NC
A12
A13
WE
NC
CE1
CE2
WE
OE
V
CC
GND
H
A18
A8
A9
A10
A11
A19
A19 A18 A17 A15 A14 A13 A16 A2 A1 A0
48-ball BGA top view
Brilliance Semiconductor, Inc.
reserves the right to modify document contents without notice.
Detailed product characteristic test report is available upon request and being accepted.
R0201-BH62UV8000
1
Revision 1.0
Jul.
2005

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