K4S640432D
CMOS SDRAM
64Mbit SDRAM
4M x 4Bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.0
June 1999
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 Jun. 1999
K4S640432D
4M x 4Bit x 4 Banks Synchronous DRAM
FEATURES
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (4K cycle)
CMOS SDRAM
GENERAL DESCRIPTION
The K4S640432D is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 4,194,304 words by 4 bits,
fabricated with SAMSUNG′s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem-
ory system applications.
ORDERING INFORMATION
Part No.
K4S640432D-TC/L75
K4S640432D-TC/L80
K4S640432D-TC/L1L
Max Freq.
133MHz(CL=3)
125MHz(CL=3)
LVTTL
100MHz(CL=3)
54
TSOP(II)
Interface Package
K4S640432D-TC/L1H 100MHz(CL=2)
K4S640432D-TC/L10 66MHz(CL=2 &3)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
LWE
LDQM
Data Input Register
Bank Select
4M x 4
Sense AMP
4M x 4
4M x 4
4M x 4
Refresh Counter
Output Buffer
Row Decoder
Row Buffer
DQi
Address Register
CLK
ADD
Column Decoder
Col. Buffer
Latency & Burst Length
LRAS
LCBR
LCKE
LRAS
LCBR
LWE
LCAS
Timing Register
Programming Register
LWCBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
DQM
*
Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.0 Jun. 1999
K4S640432D
PIN CONFIGURATION
(Top view)
V
DD
N.C
V
DDQ
N.C
DQ0
V
SSQ
N.C
N.C
V
DDQ
N.C
DQ1
V
SSQ
N.C
V
DD
N.C
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V
SS
N.C
V
SSQ
N.C
DQ3
V
DDQ
N.C
N.C
V
SSQ
N.C
DQ2
V
DDQ
N.C
V
SS
N.C/RFU
DQM
CLK
CKE
N.C
A11
A9
A8
A7
A6
A5
A4
V
SS
CMOS SDRAM
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
CLK
CS
Name
System clock
Chip select
Input Function
Active on the positive going edge to sample all inputs.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
Row/column addresses are multiplexed on the same pins.
Row address : RA
0
~ RA
11
, Column address : CA
0
~ CA
9
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active.
Data inputs/outputs are multiplexed on the same pins.
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
This pin is recommended to be left No Connection on the device.
CKE
Clock enable
A
0
~ A
11
BA
0
~ BA
1
RAS
CAS
WE
DQM
DQ
0
~
3
V
DD
/V
SS
V
DDQ
/V
SSQ
N.C/RFU
Address
Bank select address
Row address strobe
Column address strobe
Write enable
Data input/output mask
Data input/output
Power supply/ground
Data output power/ground
No connection
/reserved for future use
Rev. 0.0 Jun. 1999
K4S640432D
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
1
50
CMOS SDRAM
Unit
V
V
°C
W
mA
Note :
Permanent device damage may occur if "ASOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to V
SS
= 0V, T
A
= 0 to 70°C)
Parameter
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Symbol
V
DD
, V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
DD
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
uA
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Note
Notes :
1. V
IH
(max) = 5.6V AC.The overshoot voltage duration is
≤
3ns.
2. V
IL
(min) = -2.0V AC. The undershoot voltage duration is
≤
3ns.
3. Any input 0V
≤
V
IN
≤
V
DDQ
.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
Clock
(V
DD
= 3.3V, T
A
= 23°C, f = 1MHz, V
REF
=1.4V
±
200 mV)
Pin
Symbol
C
CLK
C
IN
C
ADD
C
OUT
Min
2.5
2.5
2.5
4.0
Max
4.0
5.0
5.0
6.5
Unit
pF
pF
pF
pF
Note
1
2
2
3
RAS, CAS, WE, CS, CKE, DQM
Address
DQ
0
~ DQ
3
Notes :
1. -75 only specify a maximum value of 3.5pF
2. -75 only specify a maximum value of 3.8pF
3. -75 only specify a maximum value of 6.0pF
Rev. 0.0 Jun. 1999
K4S640432D
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70°C)
Parameter
Symbol
Burst length = 1
t
RC
≥
t
RC
(min)
I
O
= 0 mA
CKE
≤
V
IL
(max), t
CC
= 10ns
Test Condition
CMOS SDRAM
Version
- 75 - 80 - 1H - 1L -10
Unit
Note
Operating current
(One bank active)
Precharge standby current in
power-down mode
I
CC1
I
CC2
P
70
70
65
1
1
15
65
65
mA
mA
1
I
CC2
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
Precharge standby current in
non power-down mode
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
CC2
NS
Input signals are stable
I
CC3
P
CKE
≤
V
IL
(max), t
CC
= 10ns
mA
6
3
3
25
mA
15
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
I
CC3
PS CKE & CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
mA
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
I
CC3
NS
Input signals are stable
I
O
= 0 mA
Page burst
4Banks Activated
t
CCD
= 2CLKs
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
C
L
Operating current
(Burst mode)
Refresh current
Self refresh current
I
CC4
100
95
80
80
80
mA
1
I
CC5
I
CC6
135
135 125 125 125
1
400
mA
mA
uA
2
3
4
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S640432D-TC**
4. K4S640432D-TL**
5. Unless otherwise noted, input swing IeveI is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ)
Rev. 0.0 Jun. 1999
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