K4R271669A/K4R441869A
Direct RDRAM
™
128/144Mbit RDRAM
256K x 16/18 bit x 2*16 Dependent Banks
Direct RDRAM
TM
Revision 1.02
January 2000
Page -1
Rev. 1.02 Jan. 2000
K4R271669A/K4R441869A
Revision History
Version 1.0 (July 1999) -
Preliminary
- Based on the Rambus Datasheet 1.0 ver.
Direct RDRAM
™
Version 1.01 (October 1999)
On page 1
- Delete the part numbers of low power
On page 32
- Add the data of CNFGA Register @ Figure 28
On page 33
- Add the data of CNFGB Register @ Figure 29 and correct the CORG4..0 field of CNFGB register
On page 44
- Add the Tj value from TBD to Max. 100°C @ Table 18
On page 46
- Add the
Θ
JC
value from TBD to 0.2°C/Watt @ Table 20
On page 55
- Add the current values for 356MHz and 300MHz RDRAM device
Version 1.02 (January 2000)
* Change the part number of RDRAM Component according to New Code System since ’00.Jan.1st
On page 45
- Reduce swing of V
IH,CMOS
& V
IL,CMOS
from
“0.5V
CMOS
±0.6V“
to
“0.5V
CMOS
±0.4V“
- Relax tS1 from 1.0ns to
“1.25ns“
( But, Keep tH1 as 1.0ns)
Page 0
Rev. 1.02 Jan. 2000
K4R271669A/K4R441869A
Overview
The Rambus Direct RDRAM™ is a general purpose high-
performance memory device suitable for use in a broad
range of applications including computer memory, graphics,
video, and any other application where high bandwidth and
low latency are required.
The 128/144Mbit Direct Rambus DRAMs (RDRAM
®
) are
extremely high-speed CMOS DRAMs organized as 8M
words by 16 or 18 bits. The use of Rambus Signaling Level
(RSL) technology permits 600MHz to 800MHz transfer
rates while using conventional system and board design
technologies. Direct RDRAM devices are capable of
sustained data transfers at 1.25 ns per two bytes (10ns per
sixteen bytes).
The architecture of the Direct RDRAMs allows the highest
sustained bandwidth for multiple, simultaneous randomly
addressed memory transactions. The separate control and
data buses with independent row and column control yield
over 95% bus efficiency. The Direct RDRAM's thirty-two
banks support up to four simultaneous transactions.
System oriented features for mobile, graphics and large
memory systems include power management, byte masking,
and x18 organization. The two data bits in the x18 organiza-
tion are general and can be used for additional storage and
bandwidth or for error correction.
Direct RDRAM
™
SAMSUNG 001
K4Rxxxx69A-Nxxx
SAMSUNG 001
K4Rxxxx69A-Mxxx
M
a. Normal Package
b. Mirrored Package
Figure 1: Direct RDRAM CSP Package
The 128/144Mbit Direct RDRAMs are offered in a CSP
horizontal package suitable for desktop as well as low-
profile add-in card and mobile applications.
Key Timing Parameters/Part Numbers
Speed
Organization
Bin
256Kx16x32s
a
-CG6
-CK7
-CK8
256Kx18x32s
-CG6
-CK7
-CK8
I/O
Freq.
MHz
600
711
800
600
711
800
t
RAC
(Row
Access
Time) ns
53.3
45
45
53.3
45
45
Part Number
Features
♦
Highest sustained bandwidth per DRAM device
K4R271669A-N
b
(M)C
c
G6
K4R271669A-N(M)CK7
K4R271669A-N(M)CK8
K4R441869A-N(M)CG6
K4R441869A-N(M)CK7
K4R441869A-N(M)CK8
- 1.6GB/s sustained data transfer rate
- Separate control and data buses for maximized
efficiency
- Separate row and column control buses for
easy scheduling and highest performance
- 32 banks: four transactions can take place simul-
taneously at full bandwidth data rates
♦
Low latency features
a.The
“32s"designation
indicates that this RDRAM core is composed of 32
banks which use a "split" bank architecture.
b.The
“N“
designator indicates the normal package and the
“M“
indicates the
mirrored package.
c.The
“C“
designator indicates that this RDRAM core uses Normal Power
Self Refresh.
- Write buffer to reduce read latency
- 3 precharge mechanisms for controller flexibility
- Interleaved transactions
♦
Advanced power management:
- Direct RDRAM operates from a 2.5 volt supply
- Multiple low power states allows flexibility in power
consumption versus time to transition to active state
- Power-down self-refresh
♦
Organization: 1Kbyte pages and 32 banks, x 16/18
- x18 organization allows ECC configurations or
increased storage/bandwidth
- x16 organization for low cost applications
♦
Uses Rambus Signaling Level (RSL) for up to 800MHz
operation
Page 1
Rev. 1.02 Jan. 2000
K4R271669A/K4R441869A
Pinouts and Definitions
Normal Package
This table shows the pin assignments of the normal RDRAM package.
Table 1 : a. Center-Bonded Device
(Top View For Normal Package)
12
11
10
9
8
7
6
5
4
3
2
1
ROW
COL
GND
VDD
VDD
GND
SCK
VCMOS
DQA8
*
DQA6
GND
DQA3
DQA1
VDD
DQA0
VREF
GND
CTMN
RQ7
GND
CTM
RQ1
VDD
RQ4
DQB2
GND
RQ0
DQB6
GND
DQB3
SIO0
VCMOS
DQB8
*
DQA7
GND
CMD
DQA4
VDD
DQA5
CFM
GND
DQA2
CFMN
GNDa
VDDa
RQ5
VDD
RQ6
RQ3
GND
RQ2
DQB0
VDD
DQB1
DQB4
VDD
DQB5
DQB7
GND
SIO1
GND
VDD
VDD
GND
Direct RDRAM
™
b.
Top marking
example of normal package
SAMSUNG 001
K4Rxxxx69A-Nxxx
For normal package, pin #1(ROW 1, COL A) is
located at the A1 position on the top side and
the A1 position is marked by the marker
“ “
.
Top View
A
B
C
D
E
F
G
H
J
Mirrored Package
This table shows the pin assignments of the mirrored RDRAM package.
Table 2: a.Center-Bonded Device
(Top View For Mirrored Package)
12
11
10
9
8
7
6
5
4
3
2
1
ROW
COL
GND
VDD
VDD
GND
CMD
GND
DQA7
DQA5
VDD
DQA4
DQA2
GND
CFM
VDDa
GNDa
CFMN
RQ6
VDD
RQ5
RQ2
GND
RQ3
DQB1
VDD
DQB0
DQB5
VDD
DQB4
SIO1
GND
DQB7
DQA8
*
VCMOS
SCK
DQA3
GND
DQA6
DQA0
VDD
DQA1
CTMN
GND
VREF
CTM
GND
RQ7
RQ4
VDD
RQ1
RQ0
GND
DQB2
DQB3
GND
DQB6
DQB8
*
VCMOS
SIO0
GND
VDD
VDD
GND
Chip
* DQA8/DQB8 are just used for
144Mb RDRAM. These two pins are
NC(No Connection) in 128Mb RDRAM.
b. Top marking example
of mirrored package
SAMSUNG 001
K4Rxxxx69A-Mxxx
M
A
B
C
D
E
F
G
H
J
For mirrored package, pin #1(ROW 1, COL A)
is located at the A1 postion on the top side and
the A1 position is marked by the alphabet
“
M
“
.
Page 2
Rev. 1.02 Jan. 2000
K4R271669A/K4R441869A
Direct RDRAM
™
Table 3: Pin Description
Signal
SIO1,SIO0
I/O
I/O
Type
CMOS
a
# of Pins
2
Description
Serial input/output. Pins for reading from and writing to the control
registers using a serial access protocol. Also used for power man-
agement.
Command input. Pins used in conjunction with SIO0 and SIO1 for
reading from and writing to the control registers. Also used for
power management.
Serial clock input. Clock source used for reading from and writing to
the control registers
Supply voltage for the RDRAM core and interface logic.
Supply voltage for the RDRAM analog circuitry.
Supply voltage for CMOS input/output pins.
Ground reference for RDRAM core and interface.
Ground reference for RDRAM analog circuitry.
Data byte A. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQA8 is not used by
RDRAMs with a x16 organization.
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Positive polarity.
Clock from master. Interface clock used for receiving RSL signals
from the Channel. Negative polarity
Logic threshold reference voltage for RSL signals
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Negative polarity.
Clock to master. Interface clock used for transmitting RSL signals
to the Channel. Positive polarity.
Row access control. Three pins containing control and address
information for row accesses.
Column access control. Five pins containing control and address
information for column accesses.
Data byte B. Nine pins which carry a byte of read or write data
between the Channel and the RDRAM. DQB8 is not used by
RDRAMs with a x16 organization.
CMD
I
CMOS
a
1
SCK
V
DD
V
DDa
V
CMOS
GND
GNDa
DQA8..DQA0
I
CMOS
a
1
10
1
2
13
1
I/O
RSL
b
9
CFM
CFMN
V
REF
CTMN
CTM
RQ7..RQ5 or
ROW2..ROW0
RQ4..RQ0 or
COL4..COL0
DQB8..
DQB0
I
I
RSL
b
RSL
b
1
1
1
I
I
I
I
I/O
RSL
b
RSL
b
RSL
b
RSL
b
RSL
b
1
1
3
5
9
Total pin count per package
62
a. All CMOS signals are high-true; a high voltage is a logic one and a low voltage is logic zero.
b. All RSL signals are low-true; a low voltage is a logic one and a high voltage is logic zero.
Page 3
Rev. 1.02 Jan. 2000
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