three-state drivers. The CY7C166 has an active LOW Output
Enable (OE) feature. Both devices have an automatic power-
down feature, reducing the power consumption by 65% when
deselected.
Writing to the device is accomplished when the Chip Enable
(CE) and Write Enable (WE) inputs are both LOW (and the
Output Enable (OE) is LOW for the CY7C166). Data on the
four input/output pins (I/O
0
through I/O
3
) is written into the
memory location specified on the address pins (A
0
through
A
13
).
Reading the device is accomplished by taking Chip Enable
(CE) LOW (and OE LOW for CY7C166), while Write Enable
(WE) remains HIGH. Under these conditions the contents of
the memory location specified on the address pins will appear
on the four data I/O pins.
The I/O pins stay in a high-impedance state when Chip Enable
(CE) is HIGH (or Output Enable (OE) is HIGH for CY7C166).
A die coat is used to insure alpha immunity.
Functional Description
The CY7C164 and CY7C166 are high-performance CMOS
static RAMs organized as 16,384 by 4 bits. Easy memory ex-
pansion is provided by an active LOW Chip Enable (CE) and
Logic Block Diagram
Pin Configurations
DIP
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
CE
GND
1
2
3
4
5
6 7C164
7
8
9
10
11
22
21
20
19
18
17
16
15
14
13
12
V
CC
A
4
A
3
A
2
A
1
A
0
I/O
3
I/O
2
I/O
1
I/O
0
WE
C164–3
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
CE
NC
GND
SOJ
Top View
1
2
3
4
5
6 7C164
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
4
A
3
A
2
A
1
A
0
NC
I/O
3
I/O
2
I/O
1
I/O
0
WE
C164–2
INPUT BUFFER
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
ROW DECODER
I/O
3
I/O
2
I/O
1
I/O
0
SENSE AMPS
256 x 64 x 4
ARRAY
DIP/SOJ
Top View
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
CE
OE
GND
1
24
2
23
3
22
4
21
5
20
6 7C166 19
18
7
17
8
9
16
10
15
11
14
12
13
V
CC
A
4
A
3
A
2
A
1
A
0
NC
I/O
3
I/O
2
I/O
1
I/O
0
WE
C166–1
COLUMN
DECODER
A
0
A
9
A
10
A
11
A
12
A
13
POWER
DOWN
CE
WE
(OE)
(7C166 ONLY)
C164–4
]
Selection Guide
7C164-15
7C166-15
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum Standby Current (mA)
15
115
20
7C164-20
7C166-20
20
115
20
7C164-25
7C166-25
25
105
20
7C164-35
7C166-35
35
105
20
Cypress Semiconductor Corporation
Document #: 38-05025 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134 • 408-943-2600
Revised August 24, 2001
CY7C164
CY7C166
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with
Power Applied............................................. –55°C to +125°C
Supply Voltage to Ground Potential ............... –0.5V to +7.0V
DC Voltage Applied to Outputs
in High Z State
[1]
............................................ –0.5V to +7.0V
DC Input Voltage
[1]
........................................ –0.5V to +7.0V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-Up Current.................................................... >200 mA
Operating Range
Range
Commercial
Ambient
Temperature
0°C to +70°C
V
CC
5V
±
10%
Electrical Characteristics
Over the Operating Range
7C164-15
7C166-15
Parameter
V
OH
V
OL
V
IH
V
IL
I
IX
I
OZ
I
OS
I
CC
I
SB1
I
SB2
Description
Output HIGH
Voltage
Output LOW
Voltage
Input HIGH Voltage
Input LOW
Voltage
[1]
Input Load Current
Output Leakage
Current
Output Short
Circuit Current
[2]
V
CC
Operating
Supply Current
Automatic CE
Power-Down Current
[3]
Automatic CE
Power-Down Current
[3]
GND < V
I
< V
CC
GND < V
O
< V
CC
,
Output Disabled
V
CC
= Max.,
V
OUT
= GND
V
CC
= Max.,
I
OUT
= 0 mA
Max. V
CC
, CE > V
IH,
Min. Duty Cycle = 100%
Max. V
CC
,
CE > V
CC
– 0.3V,
V
IN
> V
CC
– 0.3V
or V
IN
< 0.3V
Test Conditions
V
CC
= Min.,
I
OH
= –4.0 mA
V
CC
= Min.,
I
OL
= 8.0 mA
2.2
–0.5
–5
–5
Min.
2.4
0.4
V
CC
0.8
+5
+5
–350
115
40
20
2.2
–0.5
–5
–5
Max.
7C164-20
7C166-20
Min.
2.4
0.4
V
CC
0.8
+5
+5
–350
115
40
20
2.2
–0.5
–5
–5
Max.
7C164-25, 35
7C166-25, 35
Min.
2.4
0.4
V
CC
0.8
+5
+5
–350
105
20
20
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Capacitance
[4]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25°C, f = 1 MHz,
V
CC
= 5.0V
Max.
10
10
Unit
pF
pF
Notes:
1. Minimum voltage is equal to –3.0V for pulse durations less than 30 ns.
2. Not more than 1 output should be shorted at one time. Duration of the short circuit should not exceed 30 seconds.
3. A pull-up resistor to V
CC
on the CE input is required to keep the device deselected during V
CC
power-up, otherwise I
SB
will exceed values given.
4. Tested initially and after any design or process changes that may affect these parameters.
Document #: 38-05025 Rev. **
Page 2 of 9
CY7C164
CY7C166
AC Test Loads and Waveforms
5V
OUTPUT
30 pF
INCLUDING
JIG AND
SCOPE
(a)
Equivalent to:
R2
255
Ω
R1 481
Ω
5V
OUTPUT
5 pF
INCLUDING
JIG AND
SCOPE
(b)
R2
255
Ω
C164–5
R1 481
Ω
ALL INPUT PULSES
3.0V
GND
10%
90%
90%
10%
< 5 ns
C164–6
< 5 ns
THÉVENIN EQUIVALENT
167
Ω
OUTPUT
1.73V
Switching Characteristics
Over the Operating Range
[5]
7C164-15
7C166-15
Parameter
READ CYCLE
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
Read Cycle Time
Address to Data Valid
Output Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
[6]
CE HIGH to High Z
[6, 7]
CE LOW to Power-Up
CE HIGH to Power-Down
[8]
7C164-20
7C166-20
Min.
20
Max.
7C164-25
7C166-25
Min.
25
Max.
7C164-35
7C166-35
Min.
35
Max.
Unit
ns
35
5
35
15
3
12
5
15
0
20
25
25
25
0
0
20
15
0
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
Description
Min.
15
Max.
15
3
15
7C166
7C166
7C166
3
8
0
15
15
12
12
0
0
12
10
0
5
7
20
15
15
0
0
15
10
0
5
0
3
8
5
10
3
5
20
5
20
10
3
8
5
8
0
20
20
20
20
0
0
15
10
0
5
7
25
25
12
10
10
20
WRITE CYCLE
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
[6]
WE LOW to High Z
[6, 7]
7
Notes:
5. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
OL
/I
OH
and 30-pF load capacitance.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
for any given device. These parameters are guaranteed by design and not 100% tested.
7. t
HZCE
and t
HZWE
are specified with C
L
= 5 pF as in part (b) in AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can terminate
a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
Document #: 38-05025 Rev. **
Page 3 of 9
CY7C164
CY7C166
Switching Waveforms
Read Cycle No.1
[9, 10]
t
RC
ADDRESS
t
OHA
DATA OUT
PREVIOUS DATA VALID
t
AA
DATA VALID
C164–7
Read Cycle No. 2
[9, 11]
CE
t
ACE
OE
7C166
t
DOE
t
LZOE
HIGH IMPEDANCE
t
LZCE
V
CC
SUPPLY
CURRENT
t
PU
50%
t
PD
ICC
50%
ISB
C164–8
t
RC
t
HZOE
t
HZCE
DATA VALID
HIGH
IMPEDANCE
DATA OUT
Write Cycle No. 1 (WE Controlled)
[8, 12]
t
WC
ADDRESS
t
SCE
CE
t
SA
WE
t
SD
DATA IN
DATA
IN
VALID
t
HZWE
DATA I/O
DATA UNDEFINED
C164–9
t
AW
t
PWE
t
HA
t
HD
t
LZWE
HIGH IMPEDANCE
Notes:
9. WE is HIGH for read cycle.
10. Device is continuously selected, CE = V
IL
. (CY7C166: OE = V
IL
also).
11. Address valid prior to or coincident with CE transition LOW.
12. CY7C166 only: Data I/O will be high-impedance if OE = V
IH
.
Document #: 38-05025 Rev. **
Page 4 of 9
CY7C164
CY7C166
Switching Waveforms
(continued)
Write Cycle No. 2 (CE Controlled)
[8, 12, 13]
t
WC
ADDRESS
t
SA
CE
t
AW
t
PWE
WE
t
SD
DATA IN
DATA
IN
VALID
t
HD
t
HA
t
SCE
DATA I/O
HIGH IMPEDANCE
C164–10
Note:
13. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.
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