DSC2022
Low-Jitter Configurable Dual LVPECL Oscillator
General Description
The DSC2022 series of high performance
dual output oscillators utilize a proven silicon
MEMS technology to provide excellent jitter
and stability while incorporating additional
device functionality. The two outputs are
controlled by separate supply voltages to
allow for high output isolation. The
frequencies of the outputs can be identical or
independently derived from a common PLL
frequency source.
The DSC2022 has
provision for up to eight user-defined pre-
programmed,
pin-selectable
output
frequency combinations.
DSC2022 is packaged in a 14-pin 3.2x2.5
mm
QFN
package
and
available
in
temperature grades from Ext. Commercial to
Industrial.
Features
Low RMS Phase Jitter: <1 ps (typ)
High Stability: ±10, ±25, ±50 ppm
Wide Temperature Range
o
Industrial: -40° to 85° C
o
Ext. commercial: -20° to 70° C
High Supply Noise Rejection: -50 dBc
Two Independent LVPECL Outputs
Pin-Selectable Configurations
o
3-bit Output Frequency Combinations
Short Lead Times: 2 Weeks
Wide Freq. Range:
o
LVPECL Output: 2.3 – 460 MHz
Miniature Footprint of 3.2x2.5mm
Excellent Shock & Vibration Immunity
o
Qualified to MIL-STD-883
High Reliability
o
20x better MTF than quartz oscillators
Block Diagram
Supply Range of 2.25 to 3.6 V
Lead Free & RoHS Compliant
Applications
Storage Area Networks
o
SATA, SAS, Fibre Channel
Passive Optical Networks
o
EPON, 10G-EPON, GPON, 10G-PON
Ethernet
o
1G, 10GBASE-T/KR/LR/SR, and FCoE
HD/SD/SDI Video & Surveillance
PCI Express
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DSC2022
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MK-Q-B-P-D-12042605-3
DSC2022
Low-Jitter Configurable Dual LVPECL Oscillator
Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Pin Name
Enable
NC
NC
GND
FS0
FS1
FS2
Output1+
Output1-
Output 2-
Output 2+
VDD2
VDD
NC
Pin Type
I
NA
NA
Power
I
I
I
O
O
O
O
Power
Power
NA
Description
Enables outputs when high and disables when low
Leave unconnected or grounded
Leave unconnected or grounded
Ground
Least significant bit for frequency selection
Middle bit for frequency selection
Most significant bit for frequency selection
Positive LVPECL Output 1
Negative LVPECL Output 1
Negative LVPECL Output 2
Positive LVPECL Output 2
Power Supply 2 for LVPECL Output 2
Power Supply
Leave unconnected or grounded
coefficients required by the PLL for up to eight
different frequency combinations.
Three
control pins (FS0 – FS2) select the output
frequency combination.
Discera supports
customer defined versions of the DSC2022.
Standard frequency options are described in in
the following sections.
When Enable (pin 1) is floated or connected to
VDD, the DSC2022 is in operational mode.
Driving Enable to ground will tri-state both
output drivers (hi-impedance mode).
Operational Description
The DSC2022 is a dual output LVPECL
oscillator consisting of a MEMS resonator and
a support PLL IC.
The two outputs are
generated
through
independent
8-bit
programmable dividers from the output of the
internal PLL. Two constraints are imposed on
the output frequencies: 1) f
2
=M x f
1
/N, where
M and N are even integers between 4 and
254, 2) 1.2GHz < N x f
2
< 1.7GHz.
The actual frequencies output by the DSC2022
are controlled by an internal pre-programmed
memory (OTP).
This memory stores all
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DSC2022
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MK-Q-B-P-D-12042605-3
DSC2022
Low-Jitter Configurable Dual LVPECL Oscillator
Output Clock Frequencies
Table 1 lists the standard frequency configurations and the associated ordering information to be
used in conjunction with the ordering code. Customer defined combinations are available.
Table 1. Pre-programmed pin-selectable output frequency combinations
Ordering
Info
F0001
F0002
F0003
F0004
FXXXXX
Freq
(MHz)
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
f
OUT1
f
OUT2
Freq Select Bits [FS2, FS1, FS0] –
Default is [111]
000
106.25
25
156.25
25
150
150
100
150
001
100
100
0*
0*
0*
0*
0*
0*
010
125
125
0*
0*
0*
0*
0*
0*
011
156.25
156.25
0*
0*
0*
0*
0*
0*
100
156.25
25
156.25
25
0*
0*
0*
0*
101
156.25
125
0*
0*
0*
0*
0*
0*
110
125
25
0*
0*
0*
0*
0*
0*
111
400
200
156.25
25
0*
0*
0*
0*
Contact factory for additional configurations.
Frequency select bit are weakly tied high so if left unconnected the default setting will be [111] and
the device will output the associated frequency highlighted in
Bold.
0* – denotes invalid selection, output frequency is not specified.
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MK-Q-B-P-D-12042605-3
DSC2022
Low-Jitter Configurable Dual LVPECL Oscillator
Absolute Maximum Ratings
Item
Supply Voltage
Input Voltage
Junction Temp
Storage Temp
Soldering Temp
ESD
HBM
MM
CDM
Ordering Code
Condition
Temp Range
E: -20 to 70
I: -40 to 85
Packing
T: Tape & Reel
: Tube
Min
-0.3
-0.3
-
-55
-
-
Max
+4.0
V
DD
+0.3
+150
+150
+260
4000
400
1500
Unit
V
V
°C
°C
°C
V
DSC2022
40sec max.
F I 2
-
xxxxx
T
Freq (MHz)
See Freq. table
Package
F: 3.2x2.5mm
Stability
1: ±50ppm
2: ±25ppm
5: ±10ppm
Note: 1000+ years of data retention on internal memory
Specifications
Parameter
Supply Voltage
1
Supply Current
Supply Current
2
Frequency Stability
Aging
Startup Time
3
Input Logic Levels
Input logic high
Input logic low
Output Disable Time
4
Output Enable Time
Pull-Up Resistor
2
Output Logic Levels
Output logic high
Output logic low
(Unless specified otherwise: T=25° C)
Condition
V
DD
I
DD
I
DD
Δf
Δf
t
SU
V
IH
V
IL
t
DA
t
EN
Pull-up exists on all digital IO
40
EN pin low – outputs are disabled
EN pin high – outputs are enabled
R
L
=50Ω, F
O1
= F
O2
=156.25 MHz
Includes frequency variations due
to initial tolerance, temp. and
power supply voltage
1 year @25°C
T=25°C
0.75xV
DD
-
Min.
2.25
Typ.
21
89
Max.
3.6
23
Unit
V
mA
mA
±10
±25
±50
±5
5
-
0.25xV
DD
5
20
ppm
ppm
ms
V
ns
ns
kΩ
LVPECL Outputs
V
OH
V
OL
R
L
=50Ω
Single-Ended
t
R
t
F
f
0
SYM
J
PER
J
PH
20% to 80%
R
L
=50Ω
Single Frequency
Differential
F
O1
=F
O2
=156.25 MHz
200kHz to 20MHz @156.25MHz
100kHz to 20MHz @156.25MHz
12kHz to 20MHz @156.25MHz
2.3
48
2.5
0.25
0.38
1.7
V
DD
-1.08
-
800
250
460
52
-
V
DD
-1.55
V
mV
ps
MHz
%
ps
RMS
2
ps
RMS
Pk to Pk Output Swing
Output Transition time
4
Rise Time
Fall Time
Frequency
Output Duty Cycle
Period Jitter
5
Integrated Phase Noise
Notes:
1.
2.
3.
4.
5.
Pin 4 V
DD
should be filtered with 0.01uf capacitor.
Output is enabled if Enable pad is floated or not connected.
t
su
is time to 100PPM stable output frequency after V
DD
is applied and outputs are enabled.
Output Waveform and Test Circuit figures below define the parameters.
Period Jitter includes crosstalk from adjacent output.
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MK-Q-B-P-D-12042605-3
DSC2022
Low-Jitter Configurable Dual LVPECL Oscillator
Nominal Performance Parameters
(Unless specified otherwise: T=25° C, V
DD
=3.3 V)
2.5
156MHz LVPECL
2.0
212MHz LVPECL
320MHz LVPECL
410MHz LVPECL
1.5
1.0
0.5
Phas e Jitter ( ps RM S)
0.0
0
200
400
600
800
1000
Low-end of integration BW: x kHz to 20 MHz
LVPECL Phase jitter (integrated phase noise)
Output Waveform: LVPECL
t
R
t
F
Output
Output
80
%
50%
20%
830 mv
1/
f
o
t
EN
t
DA
V
IH
Enable
V
IL
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DSC2022
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MK-Q-B-P-D-12042605-3
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