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AMP374P6453BT1C1H

Description
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs
File Size71KB,12 Pages
ManufacturerETC
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AMP374P6453BT1C1H Overview

64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs

AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
DESCRIPTION
AVED Memory Products AMP374P6453BT1-C1H/S is a 64M bit X 72 Synchronous Dynamic RAM high density
memory module. The AVED Memory Products AMP374P6453BT1-C1H/S consists of eighteen CMOS 32M X 8 bit
with 4 banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a
168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM.
The AVED Memory Products AMP374P6453BT1-C1H/S is a Dual In-Line Memory Module and is intended for mount-
ing into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system
clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies
allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
APPLICATION
Main Memory unit for computer, Microcomputer memory,
Refresh memory for CRT.
FEATURES
Performance Ranges
Part Identification
- AMP374P6453BT1-C1H/S
8k cycles/64ms Ref, TSOP, Gold Contact Plating
- PC100 Compliant
PIN NAMES
P in N a m e
A0 - A12
BA0 - BA1
DQ0 - DQ63
CB0 - 7
CLK0 - CLK3
CKE0 - CKE1
CS0 - CS3
RAS
CAS
WE
DQM0 - 7
VDD
V ss
*V R E F
SDA
SCL
SA0 - 2
WP
DU
NC
F u n c tio n
A d d re ss In p u t (m u ltip le xe d )
S e le ct B a n k
D a ta In p u t/O u tp u t
C h e ck B it (D a ta -in /o u t)
C lo ck In p u t
C lo ck E n a b le In p u t
C h ip S e le ct In p u t
R o w A d d re ss S tro b e
C o lu m n A d d re ss S tro b e
W rite E n a b le
DQM
P o w e r S u p p ly (3 .3 V )
G ro u n d
P o w e r S u p p ly fo r R e fe re n ce
S e ria l A d d re ss D a ta I/O
S e ria l C lo ck
A d d re ss in E E P R O M
W rite P ro te ct
D o n ’t U se
N o C o n n e ctio n
Part #
Maximum Frequency/Speed
AMP374P6453BT1-C1H/S PC100MHz (10ns @ CL=2)
Burst Mode Operation
Auto & Self Refresh capability (8k cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst Length (1, 2, 4, 8 & Full Page)
Data Scramble (Sequential & Interleave)
All inputs are sampled at the positive
going edge of the system clock
Serial Presence Detect with EEPROM
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 1 of 12

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Description 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs 64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs
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