AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
DESCRIPTION
AVED Memory Products AMP374P6453BT1-C1H/S is a 64M bit X 72 Synchronous Dynamic RAM high density
memory module. The AVED Memory Products AMP374P6453BT1-C1H/S consists of eighteen CMOS 32M X 8 bit
with 4 banks Synchronous DRAMs in TSOP-II 400mil package and a 2K EEPROM in 8-pin TSSOP package on a
168-pin glass-epoxy substrate. Two 0.1uF decoupling capacitors are mounted on the printed circuit board in
parallel for each SDRAM.
The AVED Memory Products AMP374P6453BT1-C1H/S is a Dual In-Line Memory Module and is intended for mount-
ing into 168-pin edge connector sockets. Synchronous design allows precise cycle control with the use of system
clock. I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable latencies
allows the same device to be useful for a variety of high bandwidth, high performance memory system applications.
APPLICATION
Main Memory unit for computer, Microcomputer memory,
Refresh memory for CRT.
FEATURES
•
Performance Ranges
•
Part Identification
- AMP374P6453BT1-C1H/S
8k cycles/64ms Ref, TSOP, Gold Contact Plating
- PC100 Compliant
PIN NAMES
P in N a m e
A0 - A12
BA0 - BA1
DQ0 - DQ63
CB0 - 7
CLK0 - CLK3
CKE0 - CKE1
CS0 - CS3
RAS
CAS
WE
DQM0 - 7
VDD
V ss
*V R E F
SDA
SCL
SA0 - 2
WP
DU
NC
F u n c tio n
A d d re ss In p u t (m u ltip le xe d )
S e le ct B a n k
D a ta In p u t/O u tp u t
C h e ck B it (D a ta -in /o u t)
C lo ck In p u t
C lo ck E n a b le In p u t
C h ip S e le ct In p u t
R o w A d d re ss S tro b e
C o lu m n A d d re ss S tro b e
W rite E n a b le
DQM
P o w e r S u p p ly (3 .3 V )
G ro u n d
P o w e r S u p p ly fo r R e fe re n ce
S e ria l A d d re ss D a ta I/O
S e ria l C lo ck
A d d re ss in E E P R O M
W rite P ro te ct
D o n ’t U se
N o C o n n e ctio n
Part #
Maximum Frequency/Speed
AMP374P6453BT1-C1H/S PC100MHz (10ns @ CL=2)
•
•
•
•
•
Burst Mode Operation
Auto & Self Refresh capability (8k cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst Length (1, 2, 4, 8 & Full Page)
Data Scramble (Sequential & Interleave)
•
All inputs are sampled at the positive
going edge of the system clock
•
Serial Presence Detect with EEPROM
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 1 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
PIN CONFIGURATIONS (FRONT SIDE / BACK SIDE)
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Front
Vss
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
CB0
CB1
Vss
NC
NC
V
DD
WE
Pin
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
Front
DQM1
CS0
Pin
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Front
DQ18
DQ19
V
DD
DQ20
NC
*VREF
CKE1
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
Vss
CLK2
NC
WP
**SDA
**SCL
V
DD
Pin
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
Vss
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
CB5
Vss
NC
NC
V
DD
CAS
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1
RAS
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
V
DD
DQ52
NC
*VREF
NC
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
Vss
CLK3
NC
**SA0
**SA1
**SA2
V
DD
DU
Vss
A0
A2
A4
A6
A8
A10/AP
BA1
V
DD
V
DD
CLK0
Vss
DU
CS2
Vss
A1
A3
A5
A7
A9
BA0
A11
V
DD
CLK1
A12
Vss
CKE0
CS3
DQM0
DQM2
DQM3
DU
V
DD
NC
NC
CB2
CB3
Vss
DQ16
DQ17
DQM4
DQM6
DQM7
*A13
V
DD
NC
NC
CB6
CB7
Vss
DQ48
DQ49
Pins marked * are not used in this module.
Pins marked ** should be NC in the system which does not support SPD.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 2 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
PIN CONFIGURATION DESCRIPTION
Pin
CLK
CS
CKE
Name
System Clock
Chip Select
Clock Enable
Input Function
Active on the positive going edge to sam ple all inputs.
Disables or enables device operation by masking or enabling all inputs
except CLK, CKE, and DQM.
Masks system clock to freeze operation from the next clock cycle. CKE
should be enabled at least one cycle prior to new comm and. Disable
input buffers for power down in standby.
CKE should be enabled 1CLK+t ss prior to valid com mand.
Row/Column addresses are m ultiplexed on the sam e pins.
Row Address: RA0 – RA12, Column address: CA0 – CA9
Selects bank to be activated during row address latch tim e.
Selects bank for read/write during column address latch tim e.
Latches row addresses on the positive going edge of the CLK with
RAS
low.
Enables row access & precharge.
A0 - A12
Address
BA0 - BA1
Bank Select Address
RAS
Row Address Strobe
CAS
Colum n Address Strobe
Latches column addresses on the positive going edge of the CLK with
C A S
low.
Enables colum n access.
Enables write operation and row precharge.
Latches data in starting from
CAS
,
WE
active.
WE
W rite Enable
DQM0 - DQM7
DQ0 - DQ63
CB0 - 7
Data Input/Output Mask
Data Input/Output
Check bit
Makes data output Hi-Z,
tSHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte Masking)
Data inputs/outputs are m ultiplexed on the same pins.
Check bits for ECC.
WP
W rite Protect
V
DD
/Vss
Power Supply/Ground
W P pin is connected to Vss through 47KΩ Resistor. W hen W P is “high”
EEPROM program ming will be inhibited, and the entire m em ory will be
write-protected.
Power and ground for the input buffers and the core logic.
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 3 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
ABSOLUTE MAXIMUM RATINGS
Item
Voltage on any pin relative to Vss
Voltage on V
DD
supply relative to Vss
Storage Temperature
Power Dissipation
Short Circuit Current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
Tstg
Pd
IOS
Rating
-1.0 - 4.6
-1.0 - 4.6
-55 to + 150
18
50
Unit
V
V
ºC
W
mA
Note:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to higher than recommended voltage for
extended periods may affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions
(Voltage referenced to Vss=OV, Ta = 0 to 70ºC)
Item
Supply voltage
Input logic high voltage
Input logic low voltage
Output logic high voltage
Output logic low voltage
Input leakage current (Inputs)
Symbol
V
DD,
V
DDQ
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
-
-10
Typ
3.3
3.0
0
-
-
-
Max
3.6
V
DDQ
+0.3
0.8
-
0.4
10
Unit
V
V
V
V
V
µA
Notes
-
1
2
I
OH
= -2mA
I
OL
= 2mA
3
Note:1.
2.
3.
V
IH
(max) = 5.6V AC. Pulse width
≤
3ns.
V
IL
(min) = -2.0V AC. Pulse width
≤
3ns
Any input 0V
≤
V
IN
≤
V
DDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(V
DD
= 3.3V, Ta = 23ºC, f=1MHz, V
REF
= 1.4V
±
200mV)
Item
Input capacitance [A0 - A12, BA0 - BA1]
Input capacitance [
RAS
,
CAS
,
WE
]
Input capacitance [CKE0 - CKE1
]
Input capacitance [CLK0 - CLK3]
Input capacitance [
CS0 - CS3]
Input capacitance [DQM0 - DQM7]
Data input/output capacitance[DQ0 - DQ63]
Check bit [CB0 - 7]
Symbol
C
ADD
C
IN
C
CKE
C
CLK
C
CS
C
DQM
C
OUT
1
C
OUT
2
Min
50
50
28
18
18
13
13
13
Max
95
95
50
25
30
20
18
18
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 4 of 12
AVED MEMORY PRODUCTS
Where Quality & Memory Merge
AMP374P6453BT1-C1H/S
64M X 72 SDRAM DIMM with ECC based on 32M X 8, 4 Banks, 8K REFRESH, 3.3V Synchronous DRAMs WITH SPD
DC AND OPERATING CHARACTERISTICS
(Recommended operating conditions unless otherwise noted) T A = 0 to 70ºC
Symbol
ICC1*
Test Condition
Burst Length = 1
t
RC
≥
t
RC
(min)
I
OL
= 0mA
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min),
CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE & CLK
≤
V
IL
(max), t
CC
=
∞
CKE
≥
V
IH
(min),
CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
CKE
≥
V
IH
(min), CLK
≤
V
IL
(max), t
CC
=
∞
Input signals are stable
I
OL
= 0mA
Page Burst
4 Banks activated
t
CCD
= 2CLK
S
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
Version
-1H
1,260
36
36
288
252
108
108
540
450
Unit
mA
mA
ICC2P
ICC2PS
ICC2N
ICC2NS
ICC3P
ICC3PS
ICC3N
ICC3NS
ICC4
mA
mA
mA
mA
1,305
ICC5
ICC6
2,070
90
mA
mA
ICC1:
ICC2P:
ICC2PS:
ICC2N:
ICC2NS:
ICC3P:
ICC3PS:
ICC3N:
ICC3NS:
ICC4:
ICC5
ICC6:
Notes:
Operating Current (one bank active)
Precharge Standby Current in power-down mode
Precharge Standby Current in power-down mode.
Precharge Standby Current in non power-down mode.
Precharge Standby Current in non power-down mode.
Active
Active
Active
Active
Standby
Standby
Standby
Standby
Current
Current
Current
Current
in
in
in
in
power-down mode.
power-down mode.
non power-down mode (One Bank Active).
non power-down mode (One Bank Active).
Operating Current (Burst Mode)
Refresh Current
Self Refresh Current
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noted, input swing level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
).
Revision: 1.1
Revision Date: 11/2000
Document Number: 65830
Page Number: 5 of 12
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