155 Mbps ATM SAR
CONTROLLER FOR
PCI-BASED NETWORKING
APPLICATIONS
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IDT77211
Key .eatures
Full-duplex Segmentation and Reassembly (SAR) at
155 Mbps "wire-speed" (310 Mbps aggregate speed).
Performs ATM layer protocol functions.
Supports AAL5, AAL3/4, "AAL0" and "Raw Cell" formats.
Supports Constant Bit Rate (CBR)Variable Bit Rate (VBR)
and Unassigned Bit Rate (UBR) service classes.
Reassembles received CS-PDUs directly into host memory.
Two buffer pools for independant or chained reassembly
Segments CS-PDUs ready for transmission directly from
host memory.
PCI bus master interface for efficient, low latency DMA
transfers with host system.
Operates with ATM networks up to 155.52 Mbps.
Up to 16K open transmit connections.
Up to 16K simultaneous receive connections.
Glue-less integration to host system's PCI bus.
UTOPIA Interface to PHY.
Utility & Management Interface to PHY.
Standalone controller: embedded processor not required.
Supports high-performance, lowest-cost ATM NIC solution.
Supports Big/Little endian on PCI interface
Descriptions
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The IDT77211 NICStAR
™
is a member of IDT's family of products for
Asynchronous Transfer Mode (ATM) networks. The NICStAR performs
both the ATM Adaption Layer (AAL) Segmentation and Reassembly
(SAR) function and the ATM layer protocol functions.
A Network Interface Card (NIC) or internetworking product based on
the NICStAR uses host memory, rather than local memory, to reassemble
Convergence Sublayer Protocol Data Units (CS-PDUs) from ATM cell
payloads received from the network. When transmitting, as CS-PDUs
become ready, they are queued in host memory and segmented by the
NICStAR into ATM cell payloads. From this, the NICStAR then creates
complete 53-byte ATM cells which are sent through the network. The
NICStAR's on-chip PCI bus master interface provides efficient, low latency
DMA transfers with the host system, while it's UTOPIA interface provides
direct connection to PHY components used in 25.6 Mbps to 155 Mbps ATM
networks.
The IDT77211 is fabricated using state-of-the-art CMOS technology,
providing the highest levels of integration, performance and reliability, with
the low-power consumption characteristics of CMOS.
System-Level .unctional Block Diagram
32K x32
SRAM
PCI BUS
PROM
32
8
Rx UTOPIA Bus
PCI Interface
8
33MHZ
32
IDT77211
155Mbps
PCI ATM
SAR
155Mbps
PHY
2
2
Tx UTOPIA Bus
8
Utility Bus
8
4
50.0MHZ OSC.
EEPROM
3502 drw 01
MARCH 2001
1
©2001 Integrated Device Technology, Inc.
DSC-3502/6
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