AT84XCS001TP datasheet, PDF - EEWORLD Datasheet

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AT84XCS001TP: Description84 SERIES, 10 LINE TO 40 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PBGA240; Categorylogic logic; File Size89KB，8 Pages; ManufacturerAtmel (Microchip); Environmental Compliance

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AT84XCS001TP Overview

84 SERIES, 10 LINE TO 40 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PBGA240

AT84XCS001TP Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Atmel (Microchip)
Parts packaging code	BGA
package instruction	LBGA, BGA240,19X19,50
Contacts	240
Reach Compliance Code	compli
series	84
JESD-30 code	S-XBGA-B240
JESD-609 code	e4
length	25 mm
Logic integrated circuit type	MULTIPLEXER AND DEMUX/DECODER
Number of functions	1
Number of entries	1
Output times	4
Number of terminals	240
Output polarity	TRUE
Package body material	UNSPECIFIED
encapsulated code	LBGA
Encapsulate equivalent code	BGA240,19X19,50
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	260
power supply	3.3 V
Prop。Delay @ Nom-Su	2.8 ns
propagation delay (tpd)	7.1 ns
Certification status	Not Qualified
Maximum seat height	1.6 mm
Maximum supply voltage (Vsup)	3.45 V
Minimum supply voltage (Vsup)	3.15 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Terminal surface	Nickel/Palladium/Gold (Ni/Pd/Au)
Terminal form	BALL
Terminal pitch	1.27 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	25 mm

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Features

•

High-speed ADC Family Companion Chip

Selectable 1:2 or 1:4 DMUX Ratio

Power Consumption: 2.6W

LVDS Compatible Differential Data and Clock Inputs (100Ω Terminated)

LVDS Compatible Differential Data and Data Ready Outputs

Staggered or Simultaneous Data Outputs

– 11

Bit = Ports A, B, C and D Clock in Staggered Mode

Selectable Active Edge for Input and Output Clocks:

– Only Rising: CLK and DR Mode

– Rising and Falling: CLK/2 and DR/2 Mode

Fine Tuning of Input Clock Path Delay

– Compensation of External Data and Clock Path Misalignment and Skews

– Once Tuned, Setting is Valid over Full Operating Frequency and Over Full

Specified Temperature Range

Additional 11

Bit (Example: for Out-of-range Bit)

Built-in Self Test (BIST)

Stand-alone Tunable Delay Cell

Power Supplies: V

CCD

= 3.3V (Digital), V

PLUSD

= 2.5V (Outputs)

Power Consumption Reduction Mode: 1.1W

EBGA240 Package

•

10-bit 1:2/4

2.2 GHz LVDS

DMUX

AT84CS001

Summary

Screening

•

Temperature Range:

– -40° C < T

; T

< 110° C (Industrial Grade)

Applications

This DMUX enables users to process high-speed output data streams from fast ana-

log-to-digital converters down to standard FPGA processor speed.

Description

The AT84CS001 is a monolithic high-speed demultiplexer, used to lower a 10-bit data

stream of up to 2.2 Gsps guaranteed rate by a selectable 4 or 2 ratio (a 1:8 ratio may

be achieved by interleaving two DMUXes).

The DMUX is a companion chip designed to fit perfectly with all of Atmel’s high-speed

ADCs and is capable of tracking the ADC’s output sampling rate over all operating fre-

quency and temperature ranges.

Thanks to its LVDS buffers, this DMUX can easily be interfaced with standard high-

speed FPGAs (100Ω differentially terminated).

The AT84CS001 has the same footprint as Atmel’s TS81102G0 DMUX, with a very

similar pinout. Minimum re-design efforts are required to use this low-power DMUX.

An application note “Replacing Atmel’s TS81102G0 DMUX with Atmel’s AT84CS001

LVDS DMUX” reference 5413, is available to assist in migrating from the TS81102G0

to the AT84CS001.

5402AS–BDC–11/04

This is a summary document. A complete document is not

available at this time. For more information, please contact

your local Atmel sales office.

Description

The AT84CS001 is a monolithic high-speed demultiplexer (DMUX) using high-speed

Atmel technology.

It enables the user to lower a 10-bit stream of 2.2 Gsps maximum by a factor of two or

four. One can obtain a 1:8 ratio by using two interleaved AT84CS001 devices. The max-

imum input data rate is 2.2 Gsps in both 1:2 and 1:4 ratios.

The AT84CS001 DMUX is capable of processing an 11-bit data flow. The additional

11th bit (IOR/IORN) may be connected for example to the out-of-range bit of a 10-bit

ADC.

The input and output clocks as well as the input and output data are LVDS-compatible.

Digital inputs are 100Ω differentially terminated on chip. Digital output buffers shall be

terminated by a 100Ω differential ASIC load.

The improved architecture of the DMUX facilitates interfacing with high-speed ADCs

operating at up to 2.2 Gsps. No tuning of the delay between the data and clock paths

should be necessary since the data and clock paths are internally matched over the fre-

quency and specified temperature range.

However, in the case of misalignment or skews between the external clock path and the

data path, a fine delay tuning cell has been provided. Tuning may be requested for rates

exceeding 2 GHz, where the data skews are more sensitive. This tunable delay cell is

integrated in serial with the clock input. The delay is controlled by means of the CLK-

DACTRL analog control input. The tunable delay ranges from -250 ps to 250 ps for

CLKDACTRL varying from V

CCD

/3 to (2 × V

CCD

)/3.

Two modes can be selected for the clock input (CLK and CLK/2) and the clock output

(DR and DR/2):

•

CLK and DR mode: only the rising edges of the input (CLK,CLKN) and output (DR,

DRN) clocks are active. The input (or output) clock rate remains the same as the

input or output data rate.

CLK/2 and DR/2 mode: both the rising and falling edges of the input (CLK,CLKN)

and output (DR, DRN) clocks are active. The input (or output) clock rate is half the

input or output data rate.

Staggered: even and odd bits are output with half a data period delay

Simultaneous: even and odd bits are output at the same time

•

The data outputs can be received at the DMUX output in two different modes:

•

The AT84CS001 DMUX is started by the ASYNCRST control input that acts as a master

asynchronous reset for the device. Once resetted, there is no loss of synchronization

over an indefinite time period, therefore no additional incoming synchronous reset signal

is required.

The power consumption of the AT84CS001 is 2.6W and can be reduced by approxi-

mately 60% of its nominal value by means of the SLEEP control input.

A standalone delay cell is provided. It features a typical 500 ps tuning range (± 250 ps

around the center value of DACTRL analog control input).

A Built-in Self Test (BIST) is implemented for rapid debugging of the DMUX.

Die junction temperature monitoring is possible by sensing the voltage drop across a

diode implemented close to the die’s hot point after forcing a 1 mA bias current.

The AT84CS001 DMUX is a companion chip designed to fit perfectly with all of Atmel’s

high-speed ADCs.

AT84CS001

5402AS–BDC–11/04

AT84XCS001TP Related Products

	AT84XCS001TP	AT84CS001	AT84CS001TP-EB	AT84CS001VTP
Description	84 SERIES, 10 LINE TO 40 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PBGA240	84 SERIES, 10 LINE TO 40 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PBGA240	84 SERIES, 10 LINE TO 40 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PBGA240	84 SERIES, 10 LINE TO 40 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PBGA240
series	84	84	84	84
Number of functions	1	1	1	1
Number of terminals	240	240	240	240
Output polarity	TRUE	TRUE	TRUE	TRUE
surface mount	YES	Yes	Yes	YES
Terminal form	BALL	BALL	BALL	BALL
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM

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