STi5300
High-performance set-top box decoder
DATA BRIEF
DESCRIPTION
The new STi5300 MPEG-2 decoder from ST
provides a step-change in performance for pay TV
set-top boxes and digital video recorders.
Delivering 1.33 GOPS of processing power
through an ST230 VLIW CPU running at 333 MHz,
ST has ensured that manufacturers’ investment in
new products is protected as the STi5300 can
easily accommodate today’s interactive software,
and provides a platform that can support the even
more demanding applications of the future. Both
Linux and OS21 operating systems are supported,
and an MMU provides support for virtual memory
management.
The STi5300’s power comes from the VLIW
architecture of the ST230 CPU. This allows four
instructions to be executed at each CPU cycle,
dramatically
increasing
performance.
By
maintaining pin compatibility with the STi5100,
manufacturers can make use of the STi5300 with
minimal hardware redesign.
Package (27 x 27 PBGA 336 package)
xxxx
Figure 1. STi5300 low-cost interactive set-top box
IR Tx/Rx
HDD
QPSK ZIF Rx
Transport
stream in
STV0299
and
STB6000
QPSK ZIF Rx
STV0299
and
STB6000
(Optional)
SiLabs
DAA
Smart
Smart
Cards
cards
Transport
stream in
CVBS/YC
VCR
USB
port
RGB
128 Mbit
DDR
STi5300
PSTN
Flash
Rev. 1
September 2005
1/3
STI5300
FEATURES
■
ST231 VLIW host CPU
– 333 MHz, 32 Kbyte ICache,
32 Kbyte DCache
– up to 1.333 GOPs at 333 MHz
– dynamic memory management through MMU
■
■
■
■
PAL/NTSC/SECAM encoder
– RGB, CVBS, Y/C and YUV outputs with
10-bit DACs
– encoding of CGMS, Teletext, WSS, VPS,
close caption
Audio subsystem
– MPEG-1 layers I/II, MP3
– Dolby
®
Digital decoding
– Dolby Pro Logic
®
compatible output
– PCM input, mixing and sample rate
conversion
– SRS/TruSurroundXT
®
virtual surround sound
– simultaneous MPEG audio decode and
output of Dolby streams
Unified memory interface
Package 27 mm x 27 mm PBGA336
– footprint optimized for 2 layer PCBs
Dual transport stream merger
– supports DVB and
DIRECTV
®
– integrated DES-ECB, DVB and ICAM
descramblers
– NDS RASP compliant
– low-cost DVB-CI and Cable Card support
■
■
On-chip peripherals
– 4 ASCs (UARTs) with Tx and Rx FIFOs
– 6 parallel 8-bit I/O banks
– 2 smartcard interfaces and clock generators
– 3 SSCs for I
2
C/SPI master/slave interfaces
– SiLabs line side (DAA) interface
– USB 1.1/2.0 host, OHCI/EHCI compliant
– DiSEqC 2.0
™
interface
■
MPEG-2 MP@ML video decoder
– trick modes including smooth fast forward
and rewind
■
Graphics/display
– 4 display planes
– 2, 4 and 8 bpp CLUT graphics, 256 x 30 bits
(AYCBCr) CLUT entries
– 16 bpp true color graphics,
– alpha blending, antialiasing, antiflutter,
antiflicker filters
■
Enhanced security
PART NUMBERING
Table 1. Order codes
Part Number
STi5300ZUA
STi5300AUA
STi5300-Mboard
STi5300-DVB
Description
Development version
Basic DVB
Development platform
Software reference tree
REVISION HISTORY
Table 2. Revision history
Date
September-2005
Revision
1
First issue
Description of changes
2/3
STI5300
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners
© 2005 STMicroelectronics - All rights reserved
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3/3
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