Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
DESCRIPTION
The Hynix HY5V52(L)F(P) series is a 268,435,456bit CMOS Synchronous DRAM, ideally suited for the memory applica-
tions which require wide data I/O and high bandwidth. HY5V52(L)F(P) is organized as 4banks of 2,097,152x32.
HY5V52(L)F(P) is offering fully synchronous operation referenced to a positive edge of the clock. All inputs and outputs
are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth. All input and output voltage levels are compatible with LVTTL.
Programmable options include the length of pipeline (Read latency of 2 or 3), the number of consecutive read or write
cycles initiated by a single control command (Burst length of 1,2,4,8 or full page), and the burst count sequence(se-
quential or interleave). A burst of read or write cycles in progress can be terminated by a burst terminate command or
can be interrupted and replaced by a new burst read or write command on any cycle. (This pipelined design is not re-
stricted by a '2N' rule)
FEATURES
•
•
•
•
•
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Voltage : VDD, VDDQ 3.3V
All device pins are compatible with LVTTL interface
90Ball FBGA with 0.8mm of pin pitch
All inputs and outputs referenced to positive edge of
system clock
Data mask function by DQM0,1,2 and 3
•
Internal four banks operation
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Burst Read Single Write operation
Programmable CAS Latency ; 2, 3 Clocks
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•
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Auto refresh and self refresh
4096 Refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4, 8 or full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
ORDERING INFORMATION
Part No.
HY5V52(L)F-H
HY5V52(L)F-P
HY5V52(L)F-S
HY5V52(L)FP-H
HY5V52(L)FP-P
HY5V52(L)FP-S
Clock
Frequency
133MHz
100MHz
100MHz
133MHz
100MHz
100MHz
CAS
Latency
3
2
3
3
2
3
4Banks x 2Mbits
x32
LVTTL
Lead Free
Leaded
Organization
Interface
90 Ball FBGA
Note
1. HY5V52F Series : Normal power
2. HY5V52LF Series : Low Power
3. HY5V52xF Series : Leaded 90Ball FBGA
4. HY5V52xFP Series : Lead Free 90Ball FBGA
This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for
use of circuits described. No patent licenses are implied.
Rev. 0.1 / June. 2004
2
Preliminary
HY5V52(L)F(P) Series
4Banks x 2M x 32bits Synchronous DRAM
Ball FUNCTION DESCRIPTIONS
SYMBOL
CLK
CKE
CS
BA0, BA1
A0 ~ A11
Ball NAME
Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address
Strobe,
Column Address
Strobe, Write
Enable
Data Input/Output
Mask
Data Input/Output
No Connection
TYPE
INPUT
INPUT
INPUT
INPUT
INPUT
DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on
the rising edge of CLK.
Controls internal clock signal and when deactivated, the SDRAM will be
one of the states among power down, suspend or self refresh
Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
Selects bank to be read/written during CAS activity
Row Address : RA0 ~ RA11, Column Address : CA0 ~ CA8
Auto-precharge flag : A10
RAS, CAS,
WE
INPUT
RAS, CAS and WE define the operation
Refer function truth table for details
DQM0~3
DQ0 ~
DQ31
NC
I/O
SUPPLY
-
Controls output buffers in read mode and masks input data in write
mode
Multiplexed data input / output pin
No Connection
Rev. 0.1 / June. 2004
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