TC58NVG1S3BFT00/TC58NVG1S8BFT00
TENTATIVE
TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS
2
2 GBIT (256M
×
8 BIT/128M
×
16 BIT) CMOS NAND E PROM
DESCRIPTION
The TC58NVG1SxB is a single 3.3 V 2 Gbit (2,214,592,512 bits) NAND Electrically Erasable and Programmable
Read-Only Memory (NAND E
2
PROM) organized as (2048
+
64) bytes/(1024
+
32) words
×
64 pages
×
2048 blocks.
The device has a 2112-byte/1056-word static register which allow program and read data to be transferred between
the register and the memory cell array in 2112-byte increments. The Erase operation is implemented in a single
block unit (128 Kbytes
+
4 Kbytes: 2112 bytes
×
64 pages).
The TC58NVG1SxB is a serial-type memory device which utilizes the I/O pins for both address and data
input/output as well as for command inputs. The Erase and Program operations are automatically executed making
the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still
cameras and other systems which require high-density non-volatile memory data storage.
FEATURES
•
Organization
Memory cell array
Register
Page size
Block size
•
•
TC58NVG1S3B
2112
×
128K
×
8
2112
×
8
2112 bytes
(128K
+
4K) bytes
TC58NVG1S8B
1056
×
128K
×
16
1056
×
16
1056 words
(64K
+
2K) words
Modes
Read, Reset, Auto Page Program, Auto Block Erase，Status Read
Mode control
Serial input/output
Command control
Number of valid blocks
Max 2048 blocks
Min 2008 blocks
Power supply
V
CC
=
2.7 V to 3.6 V
Program/Erase Cycles
100000 Cycles (With ECC)
Access time
Cell array to register
Serial Read Cycle
Program/Erase time
Auto Page Program
Auto Block Erase
Operating current
Read (50 ns cycle)
Program (avg.)
Erase (avg.)
Standby
25
µs
max
50 ns min
200
µs/page
typ.
1.5 ms/block typ.
10 mA typ.
10 mA typ.
10 mA typ.
50
µA
max
•
•
•
•
•
•
•
Package
TC58NVG1S3BFT00 TSOP I 48-P-1220-0.50
TC58NVG1S8BFT00 TSOP I 48-P-1220-0.50
(Weight: 0.53 g typ.)
1
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
PIN ASSIGNMENT (TOP VIEW)
TC58NVG1S8BFT00
TC58NVG1S3BFT00
×
16
×
8
×
8
×
16
NC
NC
NC
NC
NC
GND
RY / BY
NC
NC
NC
NC
NC
GND
RY / BY
RE
CE
NC
NC
V
CC
V
SS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
RE
CE
NC
NC
V
CC
V
SS
NC
NC
CLE
ALE
WE
WP
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
NC
NC
NC
I/O8
I/O7
I/O6
I/O5
NC
PSL
NC
V
CC
V
SS
NC
NC
NC
I/O4
I/O3
I/O2
I/O1
NC
NC
NC
NC
V
SS
I/O16
I/O8
I/O15
I/O7
I/O14
I/O6
I/O13
I/O5
PSL
NC
V
CC
NC
NC
NC
I/O12
I/O4
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
V
SS
PINNAMES
I/O1 to I/O8
I/O9 to I/O16
I/O port
I/O port (×16)
CE
WE
RE
CLE
ALE
PSL
WP
RY/BY
GND
V
CC
V
SS
Chip enable
Write enable
Read enable
Command latch enable
Address latch enable
Power on select
Write protect
Ready/Busy
Ground
Power supply
Ground
2
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
BLOCK DIAGRAM
V
CC
V
SS
Status register
I/O1
to
I/O8
or
I/O16
CE
CLE
ALE
WE
RE
WP
PSL
RY / BY
RY / BY
Logic control
I/O
Control circuit
Address register
Column buffer
Column decoder
Command register
Data register
Sense amp
Row address decoder
Control circuit
Row address buffer
decoder
Memory cell array
HV generator
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
V
IN
V
I/O
P
D
T
SOLDER
T
STG
T
OPR
Power Supply Voltage
Input Voltage
Input /Output Voltage
Power Dissipation
Soldering Temperature (10 s)
Storage Temperature
Operating Temperature
RATING
VALUE
−
0.6 to 4.6
−
0.6 to 4.6
−
0.6 V to V
CC
+
0.3 V (
≤
4.6 V)
UNIT
V
V
V
W
°C
°C
°C
0.3
260
−
55 to 150
0 to 70
CAPACITANCE
*(Ta
=
25°C, f
=
1 MHz)
SYMB0L
C
IN
C
OUT
*
PARAMETER
Input
Output
CONDITION
V
IN
=
0 V
V
OUT
=
0 V
MIN
MAX
10
10
UNIT
pF
pF
This parameter is periodically sampled and is not tested for every device.
3
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
VALID BLOCKS
SYMBOL
N
VB
NOTE:
PARAMETER
Number of Valid Blocks
MIN
2008
TYP.
MAX
2048
UNIT
Blocks
The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.
The first block (Block 0) is guaranteed to be a valid block at the time of shipment.
The minimum number of valid blocks is guaranteed over the lifetime.
RECOMMENDED DC OPERATING CONDITIONS
SYMBOL
PARAMETER
MIN
TYP.
MAX
UNIT
V
CC
Power Supply Voltage
2.7 V
3.6 V
V
V
IH
High Level input Voltage
2.7 V
≤
V
CC
≤
3.6 V
2.0
V
CC
+
0.3
V
V
IL
*
Low Level Input Voltage
−
2 V (pulse width lower than 20 ns)
2.7 V
≤
V
CC
≤
3.6 V
−
0.3
*
0.8
V
DC CHARACTERISTICS
(Ta
=
0 to 70℃, V
CC
=
2.7 V to 3.6 V)
SYMBOL
I
IL
I
LO
PARAMETER
Input Leakage Current
Output Leakage Current
CONDITION
V
IN
=
0 V to V
CC
V
OUT
=
0 V to V
CC
PSL
=
GND or NC
I
CCO0*
Power On Reset Current
PSL
=
V
CC
, FFh command input after
Power On
CE
=
V
IL
, I
OUT
=
0 mA, tcycle
=
50 ns
MIN
TYP.
MAX
±
10
±
10
UNIT
µ
A
µ
A
10
10
10
10
10
30
mA
30
30
30
30
1
50
I
CCO1
I
CCO2
I
CCO3
I
CCS1
I
CCS2
V
OH
Serial Read Current
Programming Current
Erasing Current
Standby Current
Standby Current
High Level Output Voltage
mA
mA
mA
mA
µ
A
CE
=
V
IH
, WP
=
0 V/V
CC
CE
=
V
CC
−
0.2 V, WP
=
0 V/V
CC
I
OH
= −
0.4 mA (2.7 V
≤
V
CC
≤
3.6 V)
10
2.4
V
V
OL
Low Level Output Voltage
I
OL
=
2.1 mA (2.7 V
≤
V
CC
≤
3.6 V)
0.4
V
I
OL
( RY / BY )
*
Output current of RY / BY
V
OL
=
0.4 V (2.7 V
≤
V
CC
≤
3.6 V)
pin
8
mA
Refer to application note (2) for detail
4
2003-10-30A
TC58NVG1S3BFT00/TC58NVG1S8BFT00
AC CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(Ta
=
0 to 70℃, V
CC
=
2.7 V to 3.6 V)
SYMBOL
t
CLS
t
CLH
t
CS
t
CH
t
WP
t
ALS
t
ALH
t
DS
t
DH
t
WC
t
WH
t
WW
t
RR
t
RW
t
RP
t
RC
t
REA
t
CEA
t
CLEA
t
ALEA
t
OH
t
RHZ
t
CHZ
t
REH
t
IR
t
RHW
t
WHC
t
WHR
t
R
t
WB
t
RST
CLE Setup Time
CLE Hold Time
CE Setup Time
CE Hold Time
Write Pulse Width
ALE Setup Time
ALE Hold Time
Data Setup Time
Data Hold Time
Write Cycle Time
WE High Hold Time
WP High to WE Low
Ready to RE Falling Edge
Ready to WE Falling Edge
Read Pulse Width
Read Cycle Time
RE Access Time
CE Access Time
CLE Access Time
ALE Access Time
Data Output Hold Time
RE High to Output High Impedance
CE High to Output High Impedance
RE High Hold Time
Output-High-impedance-to- RE Falling Edge
RE High to WE Low
WE High to CE Low
WE High to RE Low
Memory Cell Array to Starting Address
WE High to Busy
Device Reset Time (Ready/Read/Program/Erase)
PARAMETER
MIN
0
10
0
10
25
0
10
20
10
50
15
100
20
20
35
50
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µ
s
NOTES
35
45
45
45
10
30
20
15
0
30
30
30
25
200
6/6/10/500
ns
µ
s
5
2003-10-30A
RF/Wirelessly
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