Am30LV0064D
Data Sheet
The Am30LV0064D is not offered for new designs. Please contact your Spansion represen-
tative for alternatives.
July 2002
The following document specifies Spansion memory products that are now offered by both Advanced
Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-
inally developed the specification, these products will be offered to customers of both AMD and
Fujitsu.
Continuity of Specifications
There is no change to this datasheet as a result of offering the device as a Spansion product. Any
changes that have been made are the result of normal datasheet improvement and are noted in the
document revision summary, where supported. Future routine revisions will occur when appropriate,
and changes will be noted in a revision summary.
Continuity of Ordering Part Numbers
AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order
these products, please use only the Ordering Part Numbers listed in this document.
For More Information
Please contact your local AMD or Fujitsu sales office for additional information about Spansion
memory solutions.
Publication Number
22203
Revision
C
Amendment
+4
Issue Date
October 19, 2004
THIS PAGE LEFT INTENTIONALLY BLANK.
Am30LV0064D
64 Megabit (8 M x 8-Bit)
CMOS 3.0 Volt-only Flash Memory with UltraNAND™ Technology
The Am30LV0064D is not offered for new designs. Please contact your Spansion representative for alternatives.
DISTINCTIVE CHARACTERISTICS
■
Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read, erase, and
program operations
— Separate V
CCQ
for 5 volt I/O tolerance
■
Automated Program and Erase
— Page program: 512 + 16 bytes
— Block erase: 8 K + 256 bytes
■
Block architecture
— 8 Kbyte blocks + 256 byte spare area
(separately erasable, readable, and programmable)
— 512 byte page + 16 byte spare area for ECC and other
system overhead information
■
Fast read and program performance (typical values)
— Read: < 7 µs initial, < 50 ns sequential
— Program: 200 µs (full page program at 400 ns/byte)
— Erase: < 2 ms/8 Kbyte block
■
Pinout and package
— Industry Standard NAND compatible pinout with 8-bit
I/O bus and control signals
— TSOP-II 44/40 pin package (standard and reverse)
with copper lead frame for higher reliability
— 40-ball FBGA package provides higher reliability and
“packing density”
■
Command set
— Basic Command set: Read Data, Read ID, Read
Status, Input Data, Program Data, Block Erase, Reset
— Superset Commands: Gapless Sequential Read
Data, Erase Suspend/Resume
■
Operation status byte
— Provides a software method of detecting program or erase
operation completion, program/erase pass/fail condition,
erase suspend status, and the write protect status
■
Operating current (typical)
— Read: 10 mA (sequential)
— Program: 10 mA
— Erase: 10 mA
— Standby: 10 µA (CMOS)
■
Block erase suspend/resume
— Suspends an erase operation to read data from, or
program data to, a block that is not being erased, then
resumes the erase operation
■
Ready/Busy# pin (RY/BY#)
— Provides a hardware method of detecting program or
erase cycle completion
■
WP# input pin
— At V
IL
, the device is protected. Program or erase
operations in the device are inhibited
— At V
IH
, the device is unprotected. Program and erase
operations are allowed
■
Minimum 10,000 program/erase cycles guaranteed
per block, without ECC (> 1 million cycles with ECC)
■
10-year data retention at 85°C
■
Industrial temperature range, –40°C to +85°C
■
100% good blocks over product lifetime
Publication#
22203
Rev:
C
Amendment/+4
Issue Date:
October 19, 2004
Refer to AMD’s Website (www.amd.com) for the latest information.
GENERAL DESCRIPTION
The Am30LV0064D is a 64 Mbit mass storage Flash
memory device, organized as 8 Kbyte (+256 byte)
blocks (1,024 blocks total), each with 16 pages of 512
(+16) bytes (16,384 pages total).
The device is suited to high-density applications in
which data is sequential and requires frequent, fast
write capability. The UltraNAND™ block and page ar-
chitecture is capable of accommodating applications
requiring IDE disk drive-compatible blocks.
Each device requires only a
single 3.0 volt power
supply
for read, program, and erase functions. Inter-
nally generated and regulated voltages are provided
for program and erase operations. A V
CCQ
pin is pro-
vided to allow 5 volts to be applied to the output buffer
logic. With 5 volt tolerant inputs, the V
CCQ
pin provides
the Flash device with 5 volt tolerant I/O.
The Am30LV0064D is entirely command set compati-
ble with industry standard NAND instructions and
timing. Commands are written to the command regis-
ter through the 8-bit I/O bus using standard NAND
write timing. Register contents serve as inputs to an
internal state-machine that controls the read, erase,
and programming circuitry. Write cycles also internally
latch addresses and data needed for the read, program-
ming, and erase operations. Reading data out of the
device is similar to reading from NAND Flash devices. The
device has an initial page read access time of 7 µs, with
subsequent byte accesses of less than 50 ns per byte.
Device programming occurs on a page basis by exe-
cuting the Input Data and Program Data command
sequences. This initiates the
Embedded Program
al-
gorithm—an internal algorithm that automatically times
the program pulse widths and verifies proper cell margin.
Device erasure is performed on a block basis and occurs
by executing the Block Erase command sequence. This
initiates the
Embedded Erase
algorithm—an internal
algorithm that automatically executes the erase operation.
During erase, the device automatically times the erase
pulse widths and verifies proper cell margin. The
block erase architecture
allows memory blocks to be
erased and reprogrammed without affecting the data
contents of other blocks. The
Erase Suspend/Erase
Resume
feature enables the user to put erase on hold
for any period of time to read data from, or program
data to, any block that is not selected for erasure. True
background erase can thus be achieved. The device is
fully erased when shipped from the factory.
The host system can detect whether a sequential read,
program, or Block Erase operation is complete by ob-
serving the RY/BY# pin or by reading the
status
register.
After a program or erase cycle has been com-
pleted, the device is ready to accept another command.
Hardware data protection
is provided by a write pro-
tect (WP#) input pin which inhibits all program and
erase operations when asserted (low).
The device offers a
standby mode
as a power-saving
feature. Once the system places the device into the
standby mode power consumption is greatly reduced.
AMD’s Flash technology combines years of Flash
memory manufacturing experience to produce the high-
est levels of quality, reliability and cost effectiveness.
4
Am30LV0064D
TABLE OF CONTENTS
Am30LV0064D ................................................. 1
Continuity of Specifications ...................................................... 1
Continuity of Ordering Part Numbers ....................................... 1
For More Information ................................................................ 1
This page left intentionally blank. . . . . . . . . . . . . 2
Erase Suspend (B0h) (Superset Command) .......................... 23
Erase Resume (D0h) (Superset Command) ........................... 23
Figure 11. Erase Suspend and Erase Resume.............................. 24
Reset Operation ..................................................................... 25
Reset (FFh) ............................................................................. 25
Figure 12. Reset............................................................................. 25
Am30LV0064D ................................................. 3
General Description . . . . . . . . . . . . . . . . . . . . . . . . 4
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 6
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . 7
Special Handling Instructions ................................................... 8
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Functional Pin Description . . . . . . . . . . . . . . . . . 10
Input/Output Pins (I/O7–I/O0) ................................................. 10
Command Latch Enable (CLE) ............................................... 10
Address Latch Enable (ALE) .................................................. 10
Chip Enable (CE#) .................................................................. 10
Read Enable (RE#) ................................................................ 10
Write Enable (WE#) ................................................................ 10
Write Protect (WP#) ................................................................ 10
Spare Area Enable (SE#) ....................................................... 10
Ready/Busy Output (RY/BY#) ................................................ 10
Device Power Supply (V
CC
) .................................................... 10
Output Buffer Power Supply (V
CCQ
) ........................................ 10
Ground (V
SS
) .......................................................................... 10
Cell Layout And Address Assignment . . . . . . . . 11
Figure 1. Mass Storage Device Cell Layout.................................... 11
Table 1. Address Assignment .........................................................11
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 26
Figure 13. Maximum Negative Overshoot Waveform .................... 26
Figure 14. Maximum Positive Overshoot Waveform...................... 26
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . 26
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 6. Test Specifications ........................................................... 27
Figure 15. Test Setup..................................................................... 27
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 28
Command, Data, and Address Input ...................................... 28
Normal Operation ................................................................... 28
Mode Selection ....................................................................... 29
Key To Switching Waveforms . . . . . . . . . . . . . . . 29
Figure 16. Command Input Cycle ..................................................
Figure 17. Address Input Cycle......................................................
Figure 18. Data Input Cycle ...........................................................
Figure 19. Serial Read Cycle .........................................................
Figure 20. Status Read Cycle ........................................................
Figure 21. Read Data.....................................................................
Figure 22. Read Data (Interrupted by CE#) ...................................
Figure 23. Read Spare Area ..........................................................
Figure 24. Sequential Read ...........................................................
Figure 25. Page Program...............................................................
Figure 26. Block Erase...................................................................
Figure 27. Erase Suspend .............................................................
Figure 28. Erase Resume ..............................................................
Figure 29. Sequential Page Program.............................................
Figure 30. ID and Manufacturer Read............................................
Figure 31. Write Protect (WP#) Timing During Power Transitions.
30
30
31
31
32
32
33
33
34
34
35
35
36
36
37
37
Ordering Information . . . . . . . . . . . . . . . . . . . . . . 12
Device Bus Operations, Command Set, And
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 13
Table 2. Am30LV0064D Device Bus Operations ............................13
Table 3. Am30LV0064D Command Set ..........................................13
Table 4. Am30LV0064D Command Definitions ..............................14
Device Operations . . . . . . . . . . . . . . . . . . . . . . . . 15
Read Operations .................................................................... 16
Read Data (00h / 01h) ............................................................ 16
Figure 2. Read Data........................................................................ 16
Gapless Read (02h) (Superset Command) ............................ 17
Figure 3. Gapless Read .................................................................. 17
Read Spare Area (50h) .......................................................... 18
Figure 4. Read Spare Area ............................................................. 18
Read ID (90h) ......................................................................... 19
Table 5. Am30LV0064D ID Codes ..................................................19
Figure 5. Read ID............................................................................ 19
Read Status (70h) .................................................................. 20
Figure 6. Device Status Register Bit Definition ............................... 20
Figure 7. Read Status ..................................................................... 20
Program Operations ............................................................... 20
Input Data (80h) ...................................................................... 20
Page Program (10h) ............................................................... 21
Figure 8. Input Data and Page Program ......................................... 21
Figure 9. Program Operations Flow Chart ...................................... 22
Erase Operations .................................................................... 23
Block Erase (60h) (D0h) ......................................................... 23
Figure 10. Block Erase.................................................................... 23
Program And Erase Characteristics . . . . . . . . . 38
Valid Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 38
TSOP II Pin Capacitance . . . . . . . . . . . . . . . . . . . 38
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 39
TS 044—44/40-Pin Standard Thin Small Outline Package II . 39
TSR044—44/40-Pin Reverse Thin Small Outline Package II . 40
FBE040—40-Ball Fine Pitch Ball Grid Array (FBGA)
8 x 15 mm package ................................................................ 41
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision A (December 1998) .................................................. 42
Revision B (December 1998) .................................................. 42
Revision B+1 (January 1999) ................................................. 42
Revision B+2 (February 1999) ................................................ 43
Revision B+3 (March 8, 1999) ................................................ 43
Revision B+4 (April 21, 1999) ................................................. 43
Revision B+5 (June 17, 1999) ................................................ 43
Revision C (May 19, 2000) ..................................................... 43
Revision C+1 (June 23, 2000) ................................................ 43
Revision C+2 (August 14, 2000) ............................................. 43
Revision C+3 (October 6, 2000) ............................................. 43
Am30LV0064D
5
FPGA/CPLD
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