v2.2
™
SX-A Automotive Family FPGAs
Specifications
•
•
•
•
12,000 to 108,000 Available System Gates
Up to 360 User-Programmable I/O Pins
Up to 2,012 Dedicated Flip-Flops
0.22µ CMOS Process Technology
•
•
•
•
•
Nonvolatile
u e
Configurable I/O Support for 3.3V PCI, 3.3V LVTTL,
2.5V LVCMOS2
Configurable Weak-Resistor Pull-up or Pull-down for
Outputs at Power-up
Individual Output Slew Rate Control
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic
Capability with Silicon Explorer II
and
Verification
Features
•
•
•
•
•
250 MHz Internal Performance
Hot-Swap Compliant I/Os
Power-up/down Friendly (No Sequencing Required
for Supply Voltages)
66 MHz PCI Compliant
Single-Chip Solution
•
•
•
•
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Actel’s Secure Programming Technology with
FuseLock™ Prevents Reverse Engineering and Design
Theft
SX-A Automotive-Grade Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Maximum User I/Os
Global Clocks
Quadrant Clocks
Boundary Scan Testing
3.3V PCI
Speed Grades
Temperature Grades*
Package
(by pin count)
PQFP
TQFP
FBGA
A54SX08A
8,000
12,000
768
512
256
512
130
3
0
Yes
Yes
Std
A
208
100, 144
144
A54SX16A
16,000
24,000
1,452
924
528
990
180
3
0
Yes
Yes
Std
A
208
100, 144
144, 256
A54SX32A
32,000
48,000
2,880
1,800
1,080
1,980
249
3
0
Yes
Yes
Std
A
208
100, 144
144, 256
A54SX72A
72,000
108,000
6,036
4,024
2,012
4,024
360
3
4
Yes
Yes
Std
A
208
–
256, 484
Note:
*The SX-A family is also offered in commercial, industrial and military temperature grades with -F, -1, -2 and -3 speed grades, in
addition to the Std speed grade. Refer to the
SX-A Family FPGAs
datasheet and
HiRel SX-A Family FPGAs
datasheet for more
details.
June 2006
© 2006 Actel Corporation
i
SX-A Automotive Family FPGAs
Ordering Information
A54SX16A
PQ
G
208
A
Application (Temperature Range)
A= Automotive (-40˚C to 125˚C)
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
FG = Fine Pitch Ball Grid Array (1.0mm pitch)
PQ = Plastic Quad Flat Pack
TQ = Thin Quad Flat Pack (1.4mm pitch)
Part Number
A54SX08A = 12,000 System Gates
A54SX16A = 24,000 System Gates
A54SX32A = 48,000 System Gates
A54SX72A = 108,000 System Gates
Note:
Automotive grade parts (A grade) devices are tested at room temperature to specifications that have been guard banded
based on characterization across the recommended operating conditions. A-grade parts are not tested at extended
temperatures. If testing to ensure guaranteed operation at extended temperatures is required, please contact your local Actel
Sales office to discuss testing options available.
Plastic Device Resources
User I/Os (including clock buffers)
Device
A54SX08A
A54SX16A
A54SX32A
A54SX72A
PQFP 208-Pin
130
175
174
171
TQFP 100-Pin
81
81
81
–
TQFP 144-Pin
113
113
113
–
FBGA 144-Pin
111
111
111
–
FBGA 256-Pin
–
180
203
203
FBGA 484-Pin
–
–
–
360
Note:
Contact your Actel sales representative for product availability.
Package Definitions:
PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, FBGA = 1.0mm Fine Pitch Ball Grid Array
ii
v2.2
Table of Contents
General Description
SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Clock Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12
Operating Conditions
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
2.5V LVCMOS2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
PCI Compliance for the Automotive-Grade SX-A Family . . . . . . . . . . . . . . . . . 1-14
SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Sample Path Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-38
Package Pin Assignments
208-Pin PQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
100-Pin TQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5
144-Pin TQFP (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8
144-Pin FBGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
256-Pin FBGA (Top View)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
484-Pin FBGA (Top View) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Export Administration Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
v2.2
iii
General Description
Actel's SX-A family of FPGAs features a sea-of-modules
architecture. SX-A devices simplify design time, enable
dramatic reductions in design costs and power
consumption, and further decrease time-to-market for
performance-intensive
applications.
With
the
automotive temperature grade support (-40°C to 125°C),
the SX-A devices can address many in-cabin telematics
and automobile interconnect applications.
Actel’s SX-A architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient
mapping of synthesized logic functions. The routing and
interconnect resources are in the metal layers above the
logic modules, providing optimal use of silicon. This
enables the entire floor of the device to be spanned with
an uninterrupted grid of fine-grained, synthesis-friendly
logic modules (or “sea-of-modules”), which reduces the
distance signals have to travel between logic modules. To
minimize signal propagation delay, SX-A devices employ
both local and general routing resources. The high-speed
local routing resources (DirectConnect and FastConnect)
enable very fast local signal propagation that is optimal
for fast counters, state machines, and datapath logic.
The general system of segmented routing tracks allows
any logic module in the array to be connected to any
other logic or I/O module. Within this system,
propagation delay is minimized by limiting the number
of antifuse interconnect elements to five (90 percent of
connections typically use only three or fewer antifuses).
The unique local and general routing structure featured
in SX-A devices gives fast and predictable performance,
allows 100% pin-locking with full logic utilization,
enables concurrent PCB development, reduces design
time, and allows designers to achieve performance goals
with minimum effort.
Further complementing SX-A’s flexible routing structure
is a hardwired, constantly loaded clock network that has
been tuned to provide fast clock propagation with
minimal clock skew. Additionally, the high performance
of the internal logic has eliminated the need to embed
latches or flip-flops in the I/O cells to achieve fast clock-
to-out or fast input set-up times. SX-A devices have easy-
to-use I/O cells that do not require HDL instantiation,
facilitating design re-use and reducing design and
verification time.
SX-A Family Architecture
Programmable Interconnect Element
The SX-A family provides efficient use of silicon by
locating the routing interconnect resources between the
top two metal layers (Figure
1-1).
This completely
eliminates the channels of routing and interconnect
resources between logic modules (as implemented on
SRAM FPGAs and previous generations of antifuse
FPGAs), and enables the entire floor of the device to be
spanned with an uninterrupted grid of logic modules.
Interconnection between these logic modules is achieved
using Actel’s patented metal-to-metal programmable
antifuse interconnect elements. The antifuses are
normally open circuit and, when programmed, form a
permanent low-impedance connection.
The extremely small size of these interconnect elements
gives the automotive-grade SX-A devices abundant
routing resources and provides excellent protection
against design pirating. Reverse engineering is virtually
impossible because it is extremely difficult to distinguish
between programmed and unprogrammed antifuses,
and since SX-A is a nonvolatile, single-chip solution,
there is no configuration bitstream to intercept.
Additionally, the interconnect (i.e., the antifuses and
metal tracks) have lower capacitance and lower
resistance than any other device of similar capacity,
leading to the fastest signal propagation in the industry.
Logic Module Design
The SX-A family architecture is described as a “sea-of-
modules” architecture because the entire floor of the
device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. Actel’s SX-A family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
The R-cell contains a flip-flop featuring asynchronous
clear, asynchronous preset, and clock enable (using the
S0 and S1 lines) control signals (Figure
1-2 on page 1-3).
The R-cell registers feature programmable clock polarity
selectable on a register-by-register basis. This provides
additional flexibility while allowing mapping of
synthesized functions into the SX-A FPGA. The clock
source for the R-cell can be chosen from either the
hardwired clock, the routed clocks, or internal logic.
v2.2
1-1
MCU
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