Low Phase Noise, Dual 1-to-8, 3.3V, 2.5V
LVPECL Output Fanout Buffer
IDT8SLVP2108I
DATASHEET
General Description
The IDT8SLVP2108I is a high-performance differential dual 1:8
LVPECL fanout buffer. The device is designed for the fanout of
high-frequency, very low additive phase-noise clock and data signals.
The IDT8SLVP2108I is characterized to operate from a 3.3V or 2.5V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the IDT8SLVP2108I ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two independent buffers with eight low skew outputs
each are available. The integrated bias voltage references enable
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Features
•
•
•
•
Two 1:8, low skew, low additive jitter LVPECL fanout buffers
Two differential clock inputs
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL, CML
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (typical)
Propagation delay: 390ps (maximum)
Low additive phase jitter, RMS: 54fs (maximum)
(f
REF
= 156.25MHz, V
PP
= 1V, 12kHz – 20MHz, V
CC
= 3.3V)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (I
EE
): 143mA
Available in Lead-free (RoHS 6), 48-Lead VFQFN package
-40°C to 85°C ambient operating temperature
•
•
•
•
•
•
•
•
Block Diagram
QA0
nQA0
QA1
nQA1
QA2
nQA2
Voltage
Reference
QA7
nQA7
QB0
nQB0
QB1
nQB1
V
CC
V
CC
PCLKA
nPCLKA
Pin Assignment
nQB2
QB2
nQB1
QB1
nQB0
QB0
nQA7
QA7
nQA6
QA6
nQA5
V
CC
QB3
nQB3
QB4
nQB4
QB5
nQB5
QB6
nQB6
QB7
nQB7
V
CC
V
REFA
Voltage
Reference
QB7
nQB7
V
REFB
IDT8SLVP2108I REV A 05/20/14
1
nPCLKB
VREFB
V
CC
V
CC
VREFA
nPCLKA
PCLKA
nc
V
EE
nc
PCLKB
PCLKB
nPCLKB
QB2
nQB2
36 35 34 33 32 31 30 29 28 27 26 25
37
24
38
23
39
22
40
21
IDT8SLVP2108I
20
41
48-lead VFQFN
42
19
7mm x 7mm x 0.8mm
43
18
package body
44
17
NL Package
45
16
Top View
46
15
47
14
48
13
1 2 3 4 5 6 7 8 9 10 11 12
V
EE
QA5
V
CC
nQA4
QA4
nQA3
QA3
nQA2
QA2
nQA1
QA1
nQA0
QA0
V
CC
©2014 Integrated Device Technology, Inc.
IDT8SLVP2108I DATASHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
1, 12
2, 11
3
4
5
6, 7, 13,
24, 37, 48
8
9
10
14, 15
16, 17
18, 19
20, 21
22, 23
25, 26
27, 28
29, 30
31, 32
33, 34
35, 36
38, 39
40, 41
42, 43
44, 45
46, 47
Name
V
EE
nc
PCLKB
nPCLKB
V
REFB
V
CC
V
REFA
nPCLKA
PCLKA
QA0, nQA0
QA1, nQA1
QA2, nQA2
QA3, nQA3
QA4, nQA4
QA5, nQA5
QA6, nQA6
QA7, nQA7
QB0, nQB0
QB1, nQB1
QB2, nQB2
QB3, nQB3
QB4, nQB4
QB5, nQB5
QB6, nQB6
QB7, nQB7
Power
Unused
Input
Input
Output
Power
Output
Input
Input
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Pullup/
Pulldown
Pulldown
Pulldown
Pullup/
Pulldown
Type
Description
Negative supply pins.
Do not connect.
Non-inverting LVPECL differential clock/data input.
Inverting LVPECL differential clock input.
Bias voltage reference for the PCLKB, nPCLKB input pair.
Power supply pins.
Bias voltage reference for the PCLKA, nPCLKA input pair.
Inverting LVPECL differential clock input.
Non-inverting LVPECL differential clock/data input.
Differential output pair A0. LVPECL interface levels.
Differential output pair A1. LVPECL interface levels.
Differential output pair A2. LVPECL interface levels.
Differential output pair A3. LVPECL interface levels.
Differential output pair A4. LVPECL interface levels.
Differential output pair A5. LVPECL interface levels.
Differential output pair A6. LVPECL interface levels.
Differential output pair A7. LVPECL interface levels.
Differential output pair B0. LVPECL interface levels.
Differential output pair B1. LVPECL interface levels.
Differential output pair B2. LVPECL interface levels.
Differential output pair B3. LVPECL interface levels.
Differential output pair B4. LVPECL interface levels.
Differential output pair B5. LVPECL interface levels.
Differential output pair B6. LVPECL interface levels.
Differential output pair B7. LVPECL interface levels.
NOTE:
Pulldown
and
Pullup
refer to internal input resistors. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
R
PULLDOWN
R
PULLUP
Parameter
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
LOW PHASE NOISE, DUAL 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
2
REV A 05/20/14
IDT8SLVP2108I DATASHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the
DC Characteristics or
AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, V
CC
Inputs, V
I
Outputs, I
O
(LVPECL)
Continuous Current
Surge Current
Input Sink/Source, I
REF
Maximum Junction Temperature, T
J,MAX
Storage Temperature, T
STG
ESD - Human Body Model (NOTE 1)
ESD - Charged Device Model (NOTE 1)
Rating
4.6V
-0.5V to V
CC
+ 0.5V
50mA
100mA
±2mA
125
C
-65C to 150C
2000V
1500V
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
QA[0:7] and QB[0:7]
terminated 50 to V
CC
– 2V
Test Conditions
Minimum
3.135
Typical
3.3V
120
595
Maximum
3.465
143
706
Units
V
mA
mA
Table 3B. Power Supply DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
V
CC
I
EE
I
CC
Parameter
Power Supply Voltage
Power Supply Current
Power Supply Current
QA[0:7] and QB[0:7]
terminated 50 to V
CC
– 2V
Test Conditions
Minimum
2.375
Typical
2.5V
113
594
Maximum
2.625
133
705
Units
V
mA
mA
REV A 05/20/14
3
LOW PHASE NOISE, DUAL 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
IDT8SLVP2108I DATASHEET
Table 3C. LVPECL DC Characteristics,
V
CC
= 3.3V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REFx
V
OH
V
OL
Parameter
Input High
Current
Input Low
Current
PCLKA, nPCLKA
PCLKB, nPCLKB
PCLKA, PCLKB
nPCLKA, nPCLKB
Test Conditions
V
CC
= V
IN
= 3.465V
V
CC
= 3.465V, V
IN
= 0V
V
CC
= 3.465V, V
IN
= 0V
I
REF
= 2mA
-10
-150
V
CC
– 1.82
V
CC
– 1.25
V
CC
– 1.70
V
CC
– 1.48
V
CC
– 1.00
V
CC
– 1.47
V
CC
– 1.27
V
CC
– 0.76
V
CC
– 1.25
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
Reference Voltage for Input
Bias
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
NOTE: V
REFx
denotes V
REFA
and V
REFB.
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
Table 3D. LVPECL DC Characteristics,
V
CC
= 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
I
IH
I
IL
V
REFx
V
OH
V
OL
Parameter
Input High Current
PCLKA, nPCLKA
PCLKB, nPCLKB
PCLKA, PCLKB
Input Low Current
nPCLKA, nPCLKB
Reference Voltage for Input Bias; NOTE 2
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Test Conditions
V
CC
= V
IN
= 2.625V
V
CC
= 2.625V, V
IN
= 0V
V
CC
= 2.625V, V
IN
= 0V
I
REF
= 2mA
-10
-150
V
CC
– 1.81
V
CC
– 1.26
V
CC
– 1.67
V
CC
– 1.47
V
CC
– 1.00
V
CC
– 1.45
V
CC
– 1.27
V
CC
– 0.75
V
CC
– 1.22
Minimum
Typical
Maximum
150
Units
µA
µA
µA
V
V
V
NOTE: V
REFx
denotes V
REFA
and V
REFB.
NOTE 1: Outputs terminated with 50 to V
CC
– 2V.
NOTE 2: For V
CC
< 3V, the use of an alternate bias voltage source is recommended.
LOW PHASE NOISE, DUAL 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
4
REV A 05/20/14
IDT8SLVP2108I DATASHEET
AC Electrical Characteristics
Table 4A. AC Electrical Characteristics,
V
CC
= 3.3V ± 5% or 2.5V ± 5%, V
EE
= 0V, T
A
= -40°C to 85°C
Symbol
f
REF
V/t
t
PD
tsk(o)
tsk(b)
tsk(p)
tsk(pp)
Parameter
Input Frequency
Input Edge Rate
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 3
Output Bank Skew; NOTE 3, 4
Pulse Skew
Part-to-Part Skew; NOTE 3, 5
f
QB0
= 500MHz, V
PP(PCLKB)
= 0.15V,
V
CMR(PCLKB)
= 1V;
f
QA7
= 62.5MHz, V
PP(PCLKA)
= 1V,
V
CMR(PCLKA)
= 1V
f
QB0
= 500MHz, V
PP(PCLKB)
= 0.15V,
V
CMR(PCLKB)
= 1V;
f
QA7
= 15.625MHz, V
PP(PCLKA)
= 1V,
V
CMR(PCLKA)
= 1V
20% to 80%
f
REF
< 1.5GHz
f
REF
1.5GHz
60
0.1
0.2
1.0
f
REF
2GHz, V
CC
= 2.5V ± 5%
f
REF
2GHz, V
CC
= 3.3V ± 5%
f
REF
2GHz, V
CC
= 2.5V ± 5%
f
REF
2GHz, V
CC
= 3.3V ± 5%
0.29
0.31
0.58
0.62
0.46
0.48
0.92
0.96
Test Conditions
PCLKA, nPCLKA and PCLKB, nPCLKB
PCLKA, nPCLKA and PCLKB, nPCLKB
PCLKA, nPCLKA to any QAx, nQAx or
PCLKB, nPCLKB to any QBx, nQBx for
V
PP
=0.1V or 0.3V
1.5
120
255
29
15
4
70
390
63
43
25
154
Minimum
Typical
Maximum
2
Units
GHz
V/ns
ps
ps
ps
ps
ps
-55
dB
t
JIT, SP
Spurious Suppression,
Coupling from QA7 to QB0
-65
dB
t
R
/ t
F
V
PP
V
CMR
V
O
(pp)
V
DIFF_OUT
Output Rise/ Fall Time;
NOTE 6
Differential Input Voltage;
NOTE 7, 8
Common Mode Input Voltage;
NOTE 7, 8, 9
Output Voltage Swing,
Peak-to-Peak
Differential Output Voltage
Swing, Peak-to-Peak
100
165
1.5
1.5
V
CC
– 0.3
0.63
0.67
1.26
1.34
ps
V
V
V
V
V
V
V
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoints.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 4: Defined as skew within a bank of outputs at the same supply voltage and with equal load conditions. Measured at the differential
crosspoints.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential crosspoints.
NOTE 6: Characterized with input signal meeting the input edge rate minimum specification.
NOTE 7: For single-ended LVCMOS input applications, please refer to the Applications Information,
Wiring the Differential Input to Accept
Single-ended Levels,
Figures 1A and 1B.
NOTE 8: V
IL
should not be less than -0.3V. V
IH
should not be higher than V
CC
.
NOTE 9: Common mode input voltage is defined at the crosspoint.
REV A 05/20/14
5
LOW PHASE NOISE, DUAL 1-TO-8, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
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