ST7538
FSK POWER LINE TRANSCEIVER
1
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FEATURES
HALF DUPLEX FREQUENCY SHIFT KEYING
(FSK) TRANSCEIVER
INTEGRATED POWER LINE DRIVER WITH
PROGRAMMABLE VOLTAGE AND CURRENT
CONTROL
PROGRAMMABLE INTERFACE:
– SYNCHRONOUS
– ASYNCHRONOUS
SINGLE SUPPLY VOLTAGE (FROM 7.5 UP TO 12.5V)
VERY LOW POWER CONSUMPTION (Iq=5 mA)
INTEGRATED 5V VOLTAGE REGULATOR
(UP TO 100mA) WITH SHORT CIRCUIT
PROTECTION
8 PROGRAMMABLE TRANSMISSION
FREQUENCIES
PROGRAMMABLE BAUD RATE UP TO 4800BPS
RECEIVING SENSITIVITY 250µVRMS
SUITABLE TO APPLICATION IN ACCORDANCE
WITH EN 50065 CENELEC SPECIFICATIONS
CARRIER OR PREAMBLE DETECTION
BAND IN USE DETECTION
PROGRAMMABLE REGISTER WITH
SECURITY CHECKSUM
MAINS ZERO CROSSING DETECTION AND
SYNCHRONIZATION
Figure 1. Package
TQFP44 Slug Down
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Table 1. Order Codes
Part Number
ST7538P
Package
TQFP44 (Slug down)
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■
■
■
WATCHDOG TIMER
2
DESCRIPTION
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Figure 2. Block Diagram
b
O
so
te
le
CD/PD
RxD
CLR/T
REG/DATA
RxTx
TxD
REGOK
ro
P
DVdd
SERIAL
INTERFACE
uc
d
DVss
CARRIER
DETECTION
PLL
s)
t(
AVss
so
b
-O
TEST1 TEST2 TEST3
BU
The ST7538 is a Half Duplex synchronous/asyn-
chronous FSK Modem designed for power line
communication network applications. It operates
from a single supply voltage and integrates a line
driver and a 5V linear regulator. The device oper-
ation is controlled by means of an internal register,
programmable through the synchronous serial in-
terface. Additional functions as watchdog, clock
output, output voltage and current control, pream-
ble detection, time-out, band in use are included.
Realized in Multipower BCD5 technology that al-
lows to integrate DMOS, Bipolar and CMOS struc-
tures in the same chip.
P
te
le
od
r
s)
t(
uc
AVdd
RxFo
TEST
BU
AGC
DIGITAL
FILTER
FSK
DEMOD
IF
FILTER
FILTER
AMPL
RAI
FILTER
CONTROL
REGISTER
CURRENT
CONTROL
TX
FILTER
VOLTAGE
CONTROL
PLI
CL
FSK
MODULATOR
DAC
ALC
Vsense
ATO
ATOP1
ATOP2
OSC
TIME BASE
ZC
OP-AMP
+
-
VREG
PAVcc
Vdc
PG
XOut
XIn
WD
TOUT
RSTO
MCLK ZCout
ZCin
C_OUT
CMINUS
CPLUS
D03IN1407A
November 2005
Rev. 5
1/30
ST7538
Figure 3. Pin Connection
(Top view)
REG_DATA
C_MINUS
C_OUT
C_PLUS
REG_OK
GND
TEST1
35
N.C.
PG
44
43
42
41
40
N.C.
39
38
37
36
CD_PD
DVSS
RXD
RxTx
TXD
GND
TOUT
CLR/T
BU
DVDD
MCLK
N.C.
34
33
32
31
30
29
28
27
26
25
24
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
VDC
RAI
RXFO
TEST2
VSENSE
AVDD
XIN
XOUT
SGND
ATO
CL
D01IN1312
Table 2. Pin Description
N°
1
Name
CD_PD
Type
Digital/Output
2
3
4
DVss
RxD
RxTx
Supply
Digital/Output
Digital/Input
with internal pull-up
5
6
7
TxD
GND
bs
O
8
9
10
11
12
l
o
TOUT
te
e
BU
Digital/Input
with internal pull-down
Supply
Digital/Output
ro
P
uc
d
s)
t(
Carrier or Preamble Detect Output.
"1" No Carrier or Preamble Detected
"0" Carrier or Preamble Detected
Digital Ground
so
b
-O
P
te
le
Description
od
r
s)
t(
uc
RSTO
TEST3
WD
ZCOUT
ZCIN
N.C.
DVSS
ATOP1
PAVSS
ATOP2
RX Data Output.
Rx or Tx mode selection input.
"1" - RX Session
"0" - TX Session
TX Data Input.
Substrate Ground (same function as PIN 41)
TX Time Out Event Detection
"1" - Time Out Event Occurred
"0" - No Time-out Event Occurred
Synchronous Mains Access Clock or
Control Register Access Clock
Band in use Output.
"1" Signal within the Programmed Band
"0" No Signal within the Programmed Band
Digital Supply Voltage
Master Clock Output
Power On or Watchdog Reset Output
CLR/T
Digital/Output
Digital/Output
DVdd
MCLK
RSTO
Supply
Digital/Output
Digital/Output
2/30
PAVCC
ST7538
Table 2. Pin Description
(continued)
N°
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
Name
TEST 3
WD
ZCOUT
ZCIN
1
NC
DVss
ATOP1
PAVss
ATOP2
PAV
CC
CL
2
ATO
SGND
XOUT
XIN
AVdd
Vsense
3
TEST2
RxFO
RAI
VDC
NC
TEST1
REGOK
Type
Digital/Input
with internal pull-down
Digital/Input
with internal pull-up
Digital/Output
Analog/Input
Floating
Supply
Power/Output
Supply
Power/Output
Supply
Analog/Input
Analog/Output
Supply
Analog I/O
Analog Input
Supply
Analog/Input
Analog/Input
Analog/Output
Analog/Input
Power
floating
Digital/Input
with internal pull-down
Digital/Output
Description
Test Input. Must be connected to DVss during Normal Operation
Watchdog input. The Internal Watchdog Counter is cleared on the
falling edges.
Zero Crossing Detection Output
Zero Crossing AC Input.
Must be connected to DVss.
Digital Ground
Power Line Driver Output
Power Analog Ground
Power Line Driver Output
Power Supply Voltage
Current Limiting Feedback.
A resistor between CL and AVss sets the PLI Current Limiting Value
Small Signal Analog Transmit Output
Analog Signal Ground
Crystal Output- External Clock Input
Crystal Oscillator Input
Analog Power supply.
Output Voltage Sensing input for the voltage control loop
Test Input must be connected SGND
Receiving Filter Output
Receiving Analog Input
5V Voltage Regulator Output
Must Be connected to DVss.
37
38
39
40
41
42
C_MINUS
4
Analog/Input
C_PLUS
5
C_OUT
GND
PG
Analog/Input
floating
Supply
O
so
b
43
44
te
le
NC
NC
ro
P
uc
d
s)
t(
Test input. Must Be connected to DVss.
Security checksum logic output
"1" - Stored data Corrupted
"0" - Stored data OK
so
b
-O
P
te
le
od
r
s)
t(
uc
Op-amp Inverting Input.
Op-amp Not Inverting Input.
Must Be connected to DVss
Op-amp Output
Substrate Ground (same function as PIN 6)
Power Good logic Output
"1" - VDC is above 4.5V
"0" - VDC is below 4.25V
Mains or Control Register Access Selector
"1" - Control Register Access
"0" - Mains Access
Must be connected to DVss.
Analog/Output
Digital/Output
REG_DATA Digital/Input
with internal pull-down
floating
<1>
<2>
<3>
<4>
<5>
If not used this pin must be connected to VDC
Cannot be left floating
Cannot be left floating
If not used this pin must be connected to VDC
If not used this pin must be tied low (SGND or PAVss or DVss)
3/30
ST7538
Table 3. Absolute Maximum Ratings
Symbol
PAV
CC
AV
dd
DV
dd
AV
ss
/DV
ss
V
I
V
O
I
O
V
sense
,
XIN,
C_MINUS,
C_PLUS,
CL
RAI, ZCIN
ATO,
RxFO,
C_OUT,
XOUT
ATOP1,2
ATOP
T
amb
T
stg
ATOP1 Pin
ATOP2 Pin
Other pins
Power Supply Voltage
Analog Supply Voltage
Digital Supply Voltage
Voltage between AV
ss
and DV
ss
Digital input Voltage
Digital output Voltage
Digital Output Current
Voltage Range at Vsense, XIN, C_MINUS, C_PLUS, CL
Inputs
Parameter
Value
-0.3 to +14
-0.3 to +5.5
-0.3 to +5.5
-0.3 to +0.3
DV
ss
- 0.3 to DV
dd
+0.3
DV
ss
- 0.3 to DV
dd
+0.3
-2 to +2
AV
ss
- 0.3 to AV
dd
+0.3
Unit
V
V
V
V
V
V
mA
V
Voltage Range at RAI, ZCIN Inputs
Voltage range at ATO, RxFO, C_OUT, XOUT Outputs
-AV
dd
- 0.3 to AV
dd
+0.3
AV
ss
- 0.3 to AV
dd
+0.3
V
V
Voltage range at Powered ATO Output
Powered ATO Output Current (*)
Operating ambient Temperature
Storage Temperature
Maximum Withstanding Voltage Range
Test Condition: CDF-AEC-Q100-002- “Human Body Model”
Acceptance Criteria: “Normal Performance”
AV
ss
- 0.3 to +PAV
cc
+0.3
400
(*) This current is intended as not repetitive pulse current
Table 4. Thermal Data
Symbol
R
th-j-amb1
R
th-j-amb2
Maximum Thermal Resistance Junction-Ambient Steady State(*)
Maximum Thermal Resistance Junction-Ambient Steady State(**)
(*) Mounted on Multilayer PCB with a dissipating surface on the bottom side of the PCB
(**) It's the same condition of the point above, without any heatsinking surface on the board.
O
so
b
te
le
ro
P
uc
d
Parameter
s)
t(
so
b
-O
P
te
le
-40 to +85
±1500
±1000
±2000
od
r
s)
t(
uc
V
°C
°C
V
V
V
mArms
-50 to 150
TQFP44
with slug
35
50
Unit
°C/W
°C/W
4/30
ST7538
Table 5. Electrical Characteristcs
(AVcc = DVcc = +5V, PAVcc =+9 V, PAVss, SGND = DVss = 0V,-40°C
≤
Tamb
≤
85°C, Fc = 86kHz, other Control
Register parameters as default value, unless otherwise specified).
Symbol
AV
CC
,
DV
CC
Parameter
Supply Voltages
DV
CC
< 4.75V
AV
CC
< 4.75V
Test Condition
Min.
4.75
0.1
0.1
7.5
Typ.
5
Max.
5.25
1.2
1.2
12.5
100
Transmission & Receiving mode
TX mode (no load)
RX mode
Maximum total current
Digital I/O
V
IH
V
IL
V
OH
V
OL
R
down
R
up
Oscillator
XOUT
SWING
XOUT Input Voltage Swing
XOUT
OFFSET
XOUT Input Voltage Offset
DC
Xtal
Xtal
ESR
Xtal
CL
Transmitter
IATO
V
ATO
XTAL Clock Duty Cycle
Crystal Oscillator frequency
External Oscillator Esr
Resistance
High Logic Level Input Voltage
Low Logic Level input Voltage
High Logic Level Output Voltage I
OH
= -2mA
Low Logic Level Output Voltage I
OL
= 2mA
Pull Down Resistor
Pull up Resistor
2
3.5
5
30
0.5
7
50
1
370
Unit
V
V
V
V
V/ms
mA
mArms
mA
mArms
V
PAV
CC
- DV
CC
PAV
CC
and DV
CC
Relation
during Power-Up Sequence
PAV
CC
- AV
CC
PAV
CC
and DV
CC
Relation
during Power-Up Sequence
PAV
cc
Power Supply Voltage
Max allowed slope during
Power-Up
AI
CC
+ DI
CC
I PAV
CC
Input Supply Current
Powered Analog Supply
Current
External Clock (see par. 3.8)
External Oscillator Stabilization
Capacitance
O
bs
V
ATODC
l
o
te
e
Output Transmitting Current on
ATO
Max Carrier Output AC Voltage R
CL
= 1.75kΩ V
sense (AC)
= 0V
V
ATO
= 2V
PP
1.75
1.7
2.3
2.1
-55
-52
Vsense connected though a
100pF cap to GND; Rcl=1.85kΩ;
R
LOAD
=1Ω (as in fig. 17)
ro
P
uc
d
s)
t(
External Clock
so
b
-O
te
le
r
P
1
od
100
100
s)
t(
uc
0.8
V
V
0.4
V
kΩ
kΩ
3
2.5
60
16
40
16
V
V
%
MHz
Ω
pF
1.5
40
1
3.5
2.5
-42
-49
mArms
V
PP
V
dB
dB
Output DC Voltage on ATO
Second Harmonic Distortion on
ATO
Third Harmonic Distortion on
ATO
Output Transmitting Current in
programmable current limiting
HD2
ATO
HD3
ATO
IATOP
250
310
370
mArms
5/30
LED Zone
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