XR16M654/654D
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
MAY 2008
REV. 1.0.0
GENERAL DESCRIPTION
The XR16M654
1
(M654) is an enhanced quad
Universal Asynchronous Receiver and Transmitter
(UART) each with 64 bytes of transmit and receive
FIFOs, programmable transmit and receive FIFO
trigger levels, automatic hardware and software flow
control, and data rates of up to 16 Mbps at 4X
sampling rate. Each UART has a set of registers that
provide the user with operating status and control,
receiver error indications, and modem serial interface
controls. An internal loopback capability allows
onboard diagnostics. The M654 is available in a 48-
pin QFN, 64-pin LQFP, 68-pin PLCC, 80-pin LQFP
and 100-pin QFP packages. The 64-pin and 80-pin
packages only offer the 16 mode interface, but the
48, 68 and 100 pin packages offer an additional 68
mode interface which allows easy integration with
Motorola processors. The XR16M654IV (64-pin)
offers three state interrupt output while the
XR16M654DIV provides continuous interrupt output.
The 100 pin package provides additional FIFO status
outputs (TXRDY# and RXRDY# A-D), separate
infrared transmit data outputs (IRTX A-D) and
channel C external clock input (CHCCLK). The
XR16M654 is compatible with the industry standard
ST16C554 and ST16C654/654D.
N
OTE
:
1 Covered by U.S. Patent #5,649,122.
FEATURES
•
Pin-to-pin compatible with ST16C454, ST16C554,
TI’s TL16C754B and NXP’s SC16C654B
•
Intel or Motorola Data Bus Interface select
•
Four independent UART channels
■
■
■
■
■
■
■
■
■
■
Register Set Compatible to 16C550
Data rates of up to 16 Mbps
64 Byte Transmit FIFO
64 Byte Receive FIFO with error tags
4 Selectable TX and RX FIFO Trigger Levels
Automatic Hardware (RTS/CTS) Flow Control
Automatic Software (Xon/Xoff) Flow Control
Progammable Xon/Xoff characters
Wireless Infrared (IrDA 1.0) Encoder/Decoder
Full modem interface
•
1.62V to 3.63V supply operation
•
Sleep Mode with automatic wake-up
•
Crystal oscillator or external clock input
APPLICATIONS
•
Portable Appliances
•
Telecommunication Network Routers
•
Ethernet Network Routers
•
Cellular Data Devices
•
Factory Automation and Process Controls
F
IGURE
1. XR16M654 B
LOCK
D
IAGRAM
1.62V to 3.6V VCC
GND
UART Channel A
UART 64 Byte TX FIFO
Regs
BRG
IR
TX & RX
ENDEC
64 Byte RX FIFO
TXB, RXB, IRTXB, DTRB#,
DSRB#, RTSB#, CTSB#,
CDB#, RIB#
TXC, RXC, IRTXC, DTRC#,
DSRC#, RTSC#, CTSC#,
CDC#, RIC#
TXD, RXD, IRTXD, DTRD#,
DSRD#, RTSD#, CTSD#,
CDD#, RID#
XTAL1
XTAL2
A2:A0
D7:D0
IOR#
IOW#
CSA#
CSB#
CSC#
CSD#
INTA
INTB
INTC
INTD
CHCCLK
TXRDY# A-D
RXRDY# A-D
Reset
16/68#
INTSEL
CLKSEL
TXA, RXA, IRTXA, DTRA#,
DSRA#, RTSA#, CTSA#,
CDA#, RIA#
Data Bus
Interface
UART Channel B
(same as Channel A)
UART Channel C
(same as Channel A)
UART Channel D
(same as Channel A)
Crystal Osc/Buffer
654 BLK
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XR16M654/654D
REV. 1.0.0
1.62V TO 3.63V QUAD UART WITH 64-BYTE FIFO
ORDERING INFORMATION
P
ART
N
UMBER
XR16M654IJ68
XR16M654IV64
XR16M654DIV64
XR16M654IQ100
XR16M654IL48
XR16M654IV80
P
ACKAGE
68-Lead PLCC
64-Lead LQFP
64-Lead LQFP
100-Lead QFP
48-pin QFN
80-Lead LQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
D
EVICE
S
TATUS
Active
Active
Active
Active
Active
Active
PIN DESCRIPTIONS
Pin Description
N
AME
48-QFN
P
IN
#
64-LQFP 68-PLCC 80-LQFP 100-QFP
T
YPE
P
IN
#
P
IN
#
P
IN
#
P
IN
#
D
ESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
IOR#
(VCC)
15
16
17
46
45
44
43
42
41
40
39
29
22
23
24
60
59
58
57
56
55
54
53
40
32
33
34
5
4
3
2
1
68
67
66
52
28
29
30
75
74
73
72
71
70
69
68
51
37
38
39
95
94
93
92
91
90
89
88
66
I
Address data lines [2:0]. These 3 address
lines select one of the internal registers in
UART channel A-D during a data bus trans-
action.
Data bus lines [7:0] (bidirectional).
I/O
I
When 16/68# pin is HIGH, the Intel bus
interface is selected and this input becomes
read strobe (active low). The falling edge
instigates an internal read cycle and
retrieves the data byte from an internal reg-
ister pointed by the address lines [A2:A0],
puts the data byte on the data bus to allow
the host processor to read it on the rising
edge.
When 16/68# pin is LOW, the Motorola bus
interface is selected and this input is not
used and should be connected to VCC.
5
FPGA/CPLD
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