CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests
are at the specified temperature and are pulsed tests, therefore: T
J
= T
C
= T
A
DC Electrical Specifications
PARAMETER
V
REF
V
REFTC
V
REFLOAD
V
RAMP
I
OSC_CHG
I
OSC_DIS
I
VDD
+V
DRV
I
VDD_OFF
V
DD_OFF
V
DD_ON
T
OT
T
HYS
I
LEAK
I
LMAX
R
DSON
R
DSONTC
I
STP
I
STN
V
PGP
V
PGN
V
PG_HI
V
PG_LO
V
OVP
V
FB
V
FB_LINE
V
FB_LOAD
V
FB_TC
I
FB
V
EN_HI
V
EN_LO
I
EN
V
DD
= V
IN
= 3.3V, T
A
= T
J
= 25°C, C
OSC
= 390pF, unless otherwise specified.
CONDITIONS
MIN
1.24
TYP
1.26
50
0 < I
REF
< 50µA
-1
1.15
0.1V < V
OSC
< 1.25V
0.1V < V
OSC
< 1.25V
V
EN
= 2.7V, F
OSC
= 120kHz
EN = 0
2.4
2.6
135
20
EN = 0, L
X
= 3.3V (low FET), L
X
= 0V
(high FET)
5
Wafer level test only
30
0.2
V
STP
= V
IN
/2
V
STN
= V
IN
/2
With respect to target output voltage
With respect to target output voltage
I
PG
= 1mA
I
PG
= -1mA
10
I
LOAD
= 0A
V
IN
= 3.3V,
∆V
IN
= 10%, I
LOAD
= 0A
0.5A < I
LOAD
< 4A
-40°C < T
A
< 85°C, I
LOAD
= 2A
V
FB
= 0V
0.977
0.992
0.5
0.5
±1
100
200
2.7
1
V
EN
= 0
-4
-2.5
1.007
6
-16
2.7
0.5
-4
2.5
2.5
4
16
-6
60
10
2
200
8
5.5
1
6.5
1.5
2.65
2.95
MAX
1.28
UNIT
V
ppm/°C
%
V
µA
mA
mA
mA
V
V
°C
°C
µA
A
mΩ
mΩ/°C
µA
µA
%
%
V
V
%
V
%
%
%
nA
V
V
µA
DESCRIPTION
Reference Accuracy
Reference Temperature Coefficient
Reference Load Regulation
Oscillator Ramp Amplitude
Oscillator Charge Current
Oscillator Discharge Current
V
DD
+V
DRV
Supply Current
V
DD
Standby Current
V
DD
for Shutdown
V
DD
for Startup
Over Temperature Threshold
Over Temperature Hysteresis
Internal FET Leakage Current
Peak Current Limit
FET On Resistance
R
DSON
Tempco
Auxiliary Supply Tracking Positive Input
Pull Down Current
Auxiliary Supply Tracking Negative Input
Pull Up Current
Positive Power Good Threshold
Negative Power Good Threshold
Power Good Drive High
Power Good Drive Low
Over Voltage Protection
Output Initial Accuracy
Output Line Regulation
Output Load Regulation
Output Temperature Stability
Feedback Input Pull Up Current
EN Input High Level
EN Input Low Level
Enable Pull Up Current
3
FN7296.2
May 13, 2005
EL7563
Closed-Loop AC Electrical Specifications
PARAMETER
F
OSC
t
SYNC
M
SS
t
BRM
t
LEB
D
MAX
DESCRIPTION
Oscillator Initial Accuracy
Minimum Oscillator Sync Width
Soft Start Slope
FET Break Before Make Delay
High Side FET Minimum On Time
Maximum Duty Cycle
(Continued)
V
S
= V
IN
= 3.3V, T
A
= T
J
= 25°C, C
OSC
= 390pF, unless otherwise specified.
CONDITIONS
MIN
310
TYP
365
25
0.5
15
150
95
MAX
420
UNIT
kHz
ns
V/ms
ns
ns
%
Typical Application Diagrams
C5
1 VREF
0.1µF
2 SGND
C4
3 COSC
R4
22Ω
C3
0.22µF
390pF
4 VDD
C2
5 VTJ
2.2nF
6 PGND
V
IN
3.3V
C1
330µF
7 PGND
8 PGND
9 PGND
10 VIN
11 VIN
12 NC
13 STP
14 STN
LX 23
LX 22
LX 21
LX 20
LX 19
LX 18
NC 17
PGND 16
PGND 15
VHI 24
C6
0.22µF
L1
4.7µH
C10
2.2nF
C7
330µF
D1
VDRV 25
D3
C9
0.1µF
V
OUT
2.5V
4A
R2
1.58kΩ
R1
1kΩ
PG 26
D2
D4
C8
0.22µF
FB 27
EN 28
28-PIN HTSSOP
4
FN7296.2
May 13, 2005
EL7563
Pin Descriptions
20-PIN SO
(0.300”)
1
2
3
4
5
6, 7
8
9
10
11, 12, 13
14, 15
16
17
18
19
20
28-PIN
HTSSOP
1
2
3
4
5
6, 7, 8, 9
10, 11
13
14
15, 16
18, 19, 20, 21,
22, 23
24
25
26
27
28
PIN NAME
VREF
SGND
COSC
VDD
VTJ
PGND
VIN
STP
STN
PGND
LX
VHI
VDRV
PG
FB
EN
PIN FUNCTION
Bandgap reference bypass capacitor; typically 0.1µF to SGND
Control circuit negative supply or signal ground
Oscillator timing capacitor (see performance curves)
Control circuit positive supply; normally connected to VIN through an RC filter
Junction temperature monitor; connected with 2.2nF to 3.3nF to SGND
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
Power supply input of the regulator; connected to the drain of the high-side NMOS power FET
Auxiliary supply tracking positive input; tied to regulator output to synchronize start up with a
second supply; leave open for stand alone operation; 2µA internal pull down current
Auxiliary supply tracking negative input; connect to output of a second supply to synchronize
start up; leave open for stand alone operation; 2µA internal pull up current
Ground return of the regulator; connected to the source of the low-side synchronous NMOS
power FET
Inductor drive pin; high current output whose average voltage equals the regulator output
voltage
Positive supply of high-side driver; boot strapped from VDRV to LX with an external 0.22µF
capacitor
Positive supply of low-side driver and input voltage for high side boot strap
Power good window comparator output; logic 1 when regulator output is within ±10% of target
output voltage
Voltage feedback input; connected to external resistor divider between VOUT and SGND; a
125nA pull-up current forces VOUT to SGND in the event that FB is floating
Chip enable, active high; a 2µA internal pull up current enables the device if the pin is left open;
a capacitor can be added at this pin to delay the start of converter
Typical Performance Curves (20 Pin SO Package)
NOTE: The 28-Pin HTSSOP Package Offers Improved Performance
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