TS27L4
Very low power precision CMOS quad operational amplifiers
Features
■
■
■
■
■
Very low power consumption: 10 µA/op
Output voltage can swing to ground
Excellent phase margin on capacitive loads
Unity gain stable
Two input offset voltage selections
SO-14
(Plastic micropackage)
DIP14
(Plastic package)
Description
The TS27L4 series are low-cost, low-power quad
operational amplifiers designed to operate with
single or dual supplies. These operational
amplifiers use the ST silicon gate CMOS process
allowing an excellent consumption-speed ratio.
These series are ideally suited for low
consumption applications.
Three power consumptions are available enabling
the best consumption-speed ratio:
I
CC
= 10 µA/amp: TS27L4 (very low power),
I
CC
= 150 µA/amp: TS27M4 (low power),
I
CC
= 1 mA/amp: TS274 (standard).
These CMOS amplifiers offer very high input
impedance and extremely low input currents. The
major advantage versus JFET devices is the very
low input current drift with temperature (see
Figure 4).
TSSOP14
(Thin shrink small outline package)
Pin connections
(top view)
Output 1 1
Inverting Input 1 2
Non-inverting Input 1 3
V
CC
+ 4
Non-inverting Input 2 5
Inverting Input 2 6
Output 2 7
+
-
+
-
-
+
-
+
14 Output 4
13 Inverting Input 4
12 Non-inverting Input 4
11 V
CC
-
10 Non-inverting Input 3
9
8
Inverting Input 3
Output 3
March 2009
Rev 3
1/15
www.st.com
15
Circuit schematics
TS27L4
1
Circuit schematics
Figure 1.
Internal block diagram
V
CC
Current
source
xI
Input
differential
Second
stage
Output
stage
Output
V
CC
E
E
2/15
TS27L4
Figure 2.
V
CC
T
24
T
25
T
26
T
6
T
8
T
27
T
5
T
10
T
15
R
2
T
28
T
1
Input
T
18
T
2
Input
R1
C1
T
11
T
12
Schematic diagram
(for 1/4 TS27L4)
T
17
T
7
T
23
T
3
Output
T
19
T
4
T
16
T
9
T
13
T
14
T
20
T
22
T
21
T
29
V
CC
Circuit schematics
3/15
Absolute maximum ratings and operating conditions
TS27L4
2
Absolute maximum ratings and operating conditions
Table 1.
Symbol
V
CC+
V
id
V
in
I
o
I
in
T
stg
Supply voltage
(1)
Differential input voltage
(2)
Input voltage
(3)
Output current for V
CC+
≥
15V
Input current
Storage temperature range
Thermal resistance junction to ambient
(4)
SO-14
TSSOP14
DIP14
Thermal resistance junction to case
(4)
SO-14
TSSOP14
DIP14
HBM: human body model
(5)
ESD
MM: machine model
(6)
CDM: charged device model
(7)
1. All values, except differential voltage are with respect to network ground terminal.
2. Differential voltages are the non-inverting input terminal with respect to the inverting input terminal.
3. The magnitude of the input and the output voltages must never exceed the magnitude of the positive
supply voltage.
4. Short-circuits can cause excessive heating and destructive dissipation. Values are typical.
5. Human body model: a 100 pF capacitor is charged to the specified voltage, then discharged through a
1.5 kΩ resistor between two pins of the device. This is done for all couples of connected pin combinations
while the other pins are floating.
6. Machine model: a 200 pF capacitor is charged to the specified voltage, then discharged directly between
two pins of the device with no external series resistor (internal resistor < 5
Ω).
This is done for all couples of
connected pin combinations while the other pins are floating.
7. Charged device model: all pins and the package are charged together to the specified voltage and then
discharged directly to the ground through only one pin. This is done for all pins.
Absolute maximum ratings
Parameter
Value
18
±18
-0.3 to 18
±30
±5
-65 to +150
105
100
80
31
32
33
1
100
1.5
Unit
V
V
V
mA
mA
°C
R
thja
°C/W
R
thjc
°C/W
kV
V
kV
Table 2.
Symbol
V
CC+
V
icm
T
oper
Operating conditions
Parameter
Supply voltage
Common mode input voltage range
Operating free-air temperature range
TS27L4C
3 to 16
0 to V
CC+
- 1.5
0 to +70
-40 to +125
TS27L4I
Unit
V
V
°C
4/15
TS27L4
Electrical characteristics
3
Table 3.
Symbol
Electrical characteristics
V
CC+
= +10 V, V
CC-
= 0 V, T
amb
= +25° C (unless otherwise specified)
TS27L4C/AC
Parameter
Min. Typ.
Input offset voltage
V
o
= 1.4V, V
ic
= 0V
TS27L4
TS27L4A
T
min
≤
T
amb
≤
T
max
TS27L4
TS27L4A
Input offset voltage drift
Input offset current
(1)
V
ic
= 5V, V
O
= 5V
T
min
≤
T
amb
≤
T
max
Input bias current
(1)
V
ic
= 5V, V
O
= 5V
T
min
≤
T
amb
≤
T
max
High level output voltage
V
id
= 100mV, R
L
= 1MΩ
T
min
≤
T
amb
≤
T
max
Low level output voltage
V
id
= -100mV
Large signal voltage gain
V
iC
= 5V, R
L
= 1MΩ, V
o
= 1V to 6V
T
min
≤
T
amb
≤
T
max
Gain bandwidth product
A
v
= 40dB, R
L
= 1MΩ, C
L
= 100pF, f
in
= 100kHz
Common mode rejection ratio
V
iC
= 1V to 7.4V, V
o
= 1.4V
Supply voltage rejection ratio
V
CC+
= 5V to 10V, V
o
= 1.4V
Supply current (per amplifier)
A
v
= 1, no load, V
o
= 5V
T
min
≤
T
amb
≤
T
max
Output short circuit current
V
o
= 0V, V
id
= 100mV
Output sink current
V
o
= V
CC
, V
id
= -100mV
Slew rate at unity gain
R
L
= 1MΩ C
L
= 100pF, V
i
= 3 to 7V
,
65
60
60
45
100
8.8
8.7
Max. Min.
Typ.
Max.
TS27L4I/AI
Unit
V
io
1.1
0.9
10
5
12
6.5
1.1
0.9
10
5
12
6.5
mV
DV
io
I
io
2
1
100
1
150
9
8.8
8.6
50
2
1
200
1
300
9
µV/°C
pA
I
ib
pA
V
OH
V
V
OL
50
mV
A
vd
60
40
100
V/mV
GBP
CMR
SVR
0.1
80
80
65
60
0.1
80
80
MHz
dB
dB
I
CC
10
15
17
10
15
18
µA
I
o
I
sink
SR
60
45
0.04
60
45
0.04
mA
mA
V/µs
5/15
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