INTEGRATED CIRCUITS
CBTV4010
10-bit DDR SDRAM mux/bus switch
Product data
File under Integrated Circuits — ICL03
2002 Feb 19
Philips
Semiconductors
Philips Semiconductors
Product data
10-bit DDR SDRAM mux/bus switch
CBTV4010
FEATURES
•
Enable signal is SSTL_2 compatible
•
Optimized for use in Double Data Rate (DDR) SDRAM
applications
•
Designed to be used with 400 Mbps/200 MHz DDR data bus
•
Switch on resistance is designed to eliminate the need for series
resistor to DDR SDRAM
•
20
Ω
on resistance
•
Internal 100
Ω
pull-down resistors
•
Low differential skew
•
Matched rise/fall slew rate
•
Low cross-talk data-data/data-DQM
•
Independent DIMM control lines
•
Latch-up protection exceeds 500 mA per JESD78
•
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
DESCRIPTION
This 10-bit bus switch is designed for 2.3 V to 2.7 V V
CC
operation
and SSTL_2 select input levels.
Each Host port pin is multiplexed to one of four DIMM port pins.
When the S pin is low the corresponding 10-bit bus switch is turned
on. The on-state connects the Host port to the DIMM port through a
20
Ω
nominal series resistance. When the S pin is high the switch is
open and a high-impedance state exists between the two ports. The
DIMM port is terminated with a 100
Ω
resistor to ground when the
S pin is high. The design is intended to have only one DIMM port
active at any time.
The part incorporates a very low cross-talk design. It has a very low
skew between outputs (< 50 ps) and low skew (< 50 ps) for rising
and falling edges. The part has optional performance in DDR data
bus applications.
Each switch has been optimized for connection to 1 or 2-bank
DIMMs.
The low internal RC time constant of the switch (20
Ω ×
7 pF) allows
data transfer to be made with minimal propagation delay.
The CBTV4010 is characterized for operation from 0 to +85
°C.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
ON
I
CCZ
PARAMETER
Propagation delay
An to Yn
Input capacitance – control pins
Channel on capacitance
Total supply current
CONDITIONS
T
amb
= 25
°C;
GND = 0 V
C
L
= 7 pF; V
CC
= 2.5 V
V
I
= 0 V or V
CC
V
in
= 1.5 V
V
CC
= 2.5 V
TYPICAL
140
1.8
7
500
UNIT
ps
pF
pF
µA
ORDERING INFORMATION
PACKAGES
TFBGA64 (Thin Fine Pitch BGA)
TEMPERATURE RANGE
0 to +85
°C
ORDER CODE
CBTV4010EE
DWG NUMBER
SOT746-1
2002 Feb 19
2
853-2315 27756
Philips Semiconductors
Product data
10-bit DDR SDRAM mux/bus switch
CBTV4010
64-BALL BGA CONFIGURATION
1
A
B
C
D
E
F
G
H
J
K
L
1DP8
0DP8
3DP7
2DP9
1DP9
0DP9
V
DD
S2
NC
2
S1
V
DD
S3
GND
3DP9
HP9
3DP8
2DP8
HP8
GND
2DP7
HP7
1DP7
0DP7
3DP6
2DP6
HP6
1DP6
GND
0DP6
3DP5
HP5
2DP5
3
NC
S0
GND
4
5
1DP0
0DP0
6
2DP0
HP0
7
3DP0
0DP1
1DP1
8
9
2DP1
HP1
10
3DP1
GND
HP2
3DP2
0DP3
HP3
GND
0DP4
HP4
3DP4
1DP5
1DP4
2DP4
0DP5
1DP3
2DP3
3DP3
11
0DP2
1DP2
2DP2
NOTE: BLANK SPACE INDICATES NO BALL
SA00589
PIN DESCRIPTION
PIN NUMBER
B6, B9, C10, F2,
F10, J2, J10, K3,
K6, K9
A2, B1, B3, C2
A5, A6, A7, A9,
A10, A11, B5, B7,
B8, B11, C11, D10,
E1, E2, E10, E11,
F1, F11, G1, G2,
G11, H2, H10, J1,
J11, K1, K4, K5,
K8, K10, K11, L1,
L2, L3, L5, L6, L7,
L9, L10, L11
B10, D2, G10, K2,
K7,
A1, B2
SYMBOL
HP0–HP9
S0–S3
0DP0–3DP3
0DP1–3DP1
0DP2–3DP2
0DP3–3DP3
0DP4–3DP4
0DP5–3DP5
0DP6–3DP6
0DP7–3DP7
0DP8–3DP8
0DP9–3DP9
GND
V
DD
NAME AND FUNCTION
Host ports
Select
DIMM ports
Ground
Positive supply voltage
FUNCTION TABLE
INPUT
S
L
H
H = High voltage level
L = Low voltage level
FUNCTION
Host port = DIMM port
Host port = Disconnect
DIMM port = 100
Ω
to GND
2002 Feb 19
3
Philips Semiconductors
Product data
10-bit DDR SDRAM mux/bus switch
CBTV4010
SIMPLIFIED SCHEMATIC, EACH FET SWITCH
LOGIC DIAGRAM (POSITIVE LOGIC)
HPx
A
Sw
nDPx
B
HP0
Sw
Sw
Sw
0DP0
1DP0
2DP0
3DP0
100
Ω
Sn
Sw
HP9
Sw
0DP9
1DP9
2DP9
SW00889
Sw
Sw
Sw
3DP9
S0
S1
S2
S3
SW00901
ABSOLUTE MAXIMUM RATINGS
1, 3
SYMBOL
V
CC
I
IK
V
I
T
stg
V
I
PARAMETER
DC supply voltage
DC input clamp current
DC input voltage range (S pin only)
2
Storage temperature range
DC input voltage range (except S pin)
2
V
I/O
< 0
CONDITIONS
RATING
–0.5 to +3.3
–50
V
CC
+ 0.3
–65 to 150
–0.5 to 3.3
UNIT
V
mA
V
°C
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
IH
V
IL
T
amb
DC supply voltage
High-level input voltage DIMM port and Host
Low-level Input voltage DIMM port and Host
Operating free-air temperature range
PARAMETER
LIMITS
Min
2.3
1.6
—
0
Typ
2.5
—
—
—
Max
2.7
—
0.9
+85
UNIT
V
V
V
°C
NOTE:
1. All unused control inputs of the device must be held at V
CC
or GND to ensure proper device operation.
2002 Feb 19
4
Philips Semiconductors
Product data
10-bit DDR SDRAM mux/bus switch
CBTV4010
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
V
IK
I
I
I
CC
C
in
C
on
r
on2
PARAMETER
Input clamp voltage
Input leakage current
Quiescent supply current
Control pin capacitance
Switch on capacitance
On-resistance
TEST CONDITIONS
Min
V
CC
= 2.3 V; I
I
= –18 mA
V
CC
= 2.5 V; V
I
= V
CC
or GND;
S = V
CC
S = GND for I
IL (test)
V
CC
= 2.5 V; I
O
= 0, V
I
= V
CC
or GND
V
I
= 2.5 V or 0
V
in
= 1.5 V
V
CC
= 2.5 V; V
A
= 0.8 V; V
B
= 1.0 V
V
CC
= 2.5 V; V
A
= 1.7 V; V
B
= 1.5 V
S
Host port
DIMM port
—
—
—
—
—
—
—
16
16
T
amb
= 0 to +85
°C
Typ
1
—
—
—
—
0.7
1.8
—
20
20
Max
–1.2
±100
±100
±100
1.5
3
10
30
30
mA
pF
pF
Ω
µA
V
UNIT
NOTES:
1. All typical values are at V
CC
= 2.5 V, T
amb
= 25
°C
2. Measured by the current between the Host and the DIMM terminals at the indicated voltages on each side of the switch.
3. Capacitance values are measured at a of 10 MHz and a bias voltage 3 V. Capacitance is not production tested.
AC CHARACTERISTICS
SYMBOL
t
pd
t
en
t
dis
t
osk
PARAMETER
Propagation delay
1
enable
disable
Output skew
Any output to any output, Waveform 4
(see note 2)
Edge skew
Difference of rising edge propagation delay
to falling edge propagation delay,
Waveform 5 (see note 2)
FROM (INPUT)
HPx or xDPx
S
n
S
n
TO (OUTPUT)
xDPx or HPx
HPx or nDPx
HPx or nDPx
V
CC
= +2.5 V
±0.2
V
Min
—
1
1
—
Typ
—
—
—
25
Max
140
2
3
50
UNIT
ps
ns
ns
ps
t
esk
—
25
50
ps
NOTES:
1. The propagation delay is based on the RC time constant of the typical on–state resistance of the switch and a load capacitance, when driven
by an ideal voltage source (zero output impedance); 20
Ω ×
7 pF.
This parameter is not production tested.
2. Skew is not production tested.
2002 Feb 19
5
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