Integrated DeviceTechnology
Integrated DeviceTechnology
Tsi721 PCIe2 to S-RIO2
Protocol Conversion Bridge
POWER MANAGEMENT | ANALOG & RF |
INTERFACE & CONNECTIVITY
| CLOCKS & TIMING | MEMORY & LOGIC | TOUCH & USER INTERFACE | VIDEO & DISPLAY | AUDIO
FEATURES
• x4 PCIe V2.1 to x4 S-RIO V2.1
• Single port: x4, x2 or x1 support
• 1.25, 2.5, 3.125 and 5 Gbaud support
• 8 DMA and Messaging channels/engines each
capable of supporting full 20 Gbaud I/O
• 8Kbyte packet buffering per DMA and
Messaging Channel
• 20 Gaud line rate performance for 64 byte or
larger packets, max TLP payload 256 bytes,
max block DMA 64 Mbyte
• PCI Express non-transparent bridging for
transaction mapping
• Lane reversal
• Automatic Polarity inversion for PCI Express
• Typical power 2W
• Reach Support: 60 cm over 2 connectors
• 100, 125, 156.25 MHz S-RIO and PCIe Endpoint
compatible clocking options
• JTAG 1149.1 and 1149.6
• 13x13 mm FCBGA
• Industrial and Commercial options
BENEFITS
• Use RapidIO’s peer to peer networking
performance with PCIe enabled microprocessors
and Network Processors
• Design Heterogeneous systems with RapidIO
and PCI Express
• Execute large block data transfers without
processor involvement for real time signal
processing tasks
• No in house NRE required to develop bridging
solutions with FPGA or ASIC
• Save on FPGA development, board space and
power with Tsi721 solution
• Superior cost and form factor to Ethernet
and Infiniband NICs
• Use a mix of RapidIO and PCIe based payload
processing cards in the same chassis
• Map Block DMA transfers to RapidIO messages
with dedicated DMA engine per messaging
channel, ideal in highly data intensive signal
processing applications
• Superior and deterministic performance and
latency in embedded peer to peer networks
compared to Ethernet and Infiniband solutions
• Provides Server Network Interface Controller
Functionality
TARGET APPLICATIONS
• Defense & Aerospace: Radar, sonar and
navigations systems
• Server and High Performance Computing
• Medical Imaging: CT Scanners, MRIs
• Video: Teleconferencing and Head End
• Wireless: Design Baseband Cards with PCIe
enabled MAC/Control processor with S-RIO
DSPs, S-RIO FPGA and S-RIO backplane
IDT
|
THE ANALOG + DIGITAL COMPANY
IDT is the industry’s leading supplier of RapidIO
®
and PCI Express
®
Interconnect solutions, provid-
ing a broad portfolio of switches, bridges, IP and development platforms for defense, aerospace,
video, imaging and wireless markets. The Tsi721 is IDT’s solution for hardware based PCIe Gen 2
to RapidIO Gen 2 protocol conversion in a bridging device
Tsi721 Device Overview
The Tsi721 converts from PCIe to RapidIO and vice versa and provides full line rate bridging at 20 Gbaud. Us-
ing the Tsi721 designers can develop heterogeneous systems that leverage the peer to peer networking per-
formance of RapidIO while at the same time using multiprocessor clus¬ters that may only be PCIe enabled.
Using the Tsi721, applications that require large amounts of data transferred efficiently without processor
involvement can be executed using the full line rate block DMA+Messaging engines of the Tsi721.
Protocol Conversion and Bridging Functionality
Key to the Tsi721 is the hardware bridging functionality that converts and maps PCIe transactions
to RapidIO. The Tsi721 supports PCIe non transparent bridging for transaction mapping. The Tsi721
has both RapidIO and PCIe endpoints embedded in the bridge. With respect to bridging large
data transfers, each of the DMA/Messaging channels can buffer up to 8K byte PCIe block DMA
trans¬fers on the PCIe side and messages totaling 32 256 byte packets on the RapidIO side. This is
all achieved in a significantly smaller form factor when compared to alternative implementations
in FPGAs or Ethernet/Inifinband NIC devices.
Tsi721 PRODUCT BRIEF
1
Tsi721 PCIe2 to S-RIO2 Protocol Conversion Bridge
POWER MANAGEMENT | ANALOG & RF |
INTERFACE & CONNECTIVITY
| CLOCKS & TIMING | MEMORY & LOGIC | TOUCH & USER INTERFACE | VIDEO & DISPLAY | AUDIO
Integrated DeviceTechnology
Defense/Aerospace Application
Server
CPS-1848
48-lane Switch
CPS-1848
48-lane Switch
1
PCIe Payload Card
with Rapid IO Bridge
x86
CPU
Tsi721
PCIe2 to S-RIO2
S-RIO Switch
18x1,18x2,
12x4
CPS-1432
x86
CPU
Tsi721
PCIe2 to S-RIO2
CPS-1432 / 32-lane
CPS-1432 / 32-lane
Rapid IO Switch Card
up to 24 x 4 S-RIO
CPS-1848
S-RIO Switch
18x1, 18x2, 12x4
4x4 S-RIO
to Backplane
Tsi-721
PCIe 2 to
S-RIO 2
1-16 CPU
per node
Tsi-721
PCIe 2 to
S-RIO 2
16 - 1000
Server Compute
Nodes Per System
Tsi-721
PCIe 2 to
S-RIO 2
1-16 CPU
per node
Tsi-721
PCIe 2 to
S-RIO 2
x86 CPU
x86 CPU
x86 CPU
x86 CPU
PCI EXPRESS FEATURES
• Max-Packet-Size 128Byte or256Byte
• Max Read Request Size 4KByte
• Up to 32 simultaneous transactions
• 12K input, output buffers
• Store and forward from PCIe to RapidIO
• Support for End-to-End CRC (ECRC)
• Support for MSI-X with 70 vectors
• Support for legacy INTx/MSI
• Support for 32b and 64b addressing
• Support for Internal Error Reporting (IER) and
Advanced Error Reporting (AER)
• PCIe spec compliant power management
• Boot from PCIe enabled processor or EEPROM
SERIAL RAPIDIO FEATURES
• Line rate performance with 64Byte and larger
S-RIO packets with up to 256 outstanding
transactions
• 8KB S-RIO ingress buffer (256x32 byte)
• Support for 34b, 50b, 66b addressing
• Support for 8b, 16b S-RIO Transport ids
• Support for 8 levels of priority using 4 S-RIO
standard priorities plus CRF bit
• S-RIO messaging (type11) implemented with
4KB max message
• Store and Forward RapidIO to PCIe
• Support for following SRIO transaction types:
– NRead, SWrite, NWrite, NWrite_R
– Port Write
– Doorbell
– Maintenance Read, Maintenance Write
– Message
• Access to all Tsi721 registers via SRIO
maintenance transactions
• Hot Insertion/Extraction Support
Imaging/Video Application
DSP/FPGA
S-RIO
DSP/FPGA
S-RIO
DSP/FPGA
S-RIO
DSP/FPGA
S-RIO
x4 PCIe
Tsi721
PCIe
to S-RIO
Gen 1 or 2
x4
S-RIO
x4
S-RIO
RapidIO
Gen 2
Switch
x4
S-RIO
x4
S-RIO
x4
S-RIO
Wireless Application
x4 S-RIO Backplane
p
Antenna Interface CPRI/OBSAI
x4 S-RIO
Tsi721
PCIe2 to S-RIO2
x4 PCIe
S-RIO
x4 S-RI
FPGA S-RIO
CPRI Interface
OFDMA PHY
DSP S-RIO
Turbo Decode
+ Viterbi
Acceleration
Rapid IO
Gen2
Switch
CPS-1616
X86 CPU Control Plane, MAC Layer,
4x4 MIMO, Multiple Sectors
x4 S-RIO
DISCLAIMER Integrated Device Technology, Inc. (IDT) and its subsidiaries reserve the right to modify the products and/or specifications described herein at any time and at IDT’s sole discretion. All information in this document, including descriptions of product features and performance, is subject to change without notice. Performance specifications and the operating parameters
of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT’s products for any particular purpose, an implied
warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably
expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are registered trademarks of IDT. Other trademarks and service marks used herein, including protected names, logos and designs, are the property of IDT or their respective third party owners. © Copyright 2010. All rights reserved.
PB_TSI721_REVD0711
IDT
| THE ANALOG + DIGITAL COMPANY
Tsi721 PRODUCT BRIEF
2
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