NB3N121K
3.3V Differential 1:21
Fanout Clock and Data
Driver with HCSL Outputs
Description
The NB3N121K is a differential 1:21 Clock and Data fanout buffer
with High−speed Current Steering Logic (HCSL) outputs optimized
for ultra low propagation delay variation. The NB3N121K is designed
with HCSL PCI Express clock distribution and FBDIMM applications
in mind.
Inputs can directly accept differential LVPECL, HCSL, and LVDS
signals per Figures 7, 8, and 9. Single ended LVPECL, HCSL,
LVCMOS, or LVTTL levels are accepted with a proper external V
th
reference supply per Figures 4 and 10. Input pins incorporate separate
internal 50
W
termination resistors allowing additional single ended
system interconnect flexibility.
Output drive current is set by connecting a 475
W
resistor from
IREF (Pin 1) to GND per Figure 6. Outputs can also interface to
LVDS receivers when terminated per Figure 11.
The NB3N121K specifically guarantees low output–to–output
skew. Optimal design, layout, and processing minimize skew within a
device and from device to device. System designers can take
advantage of the NB3N121K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
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QFN−52
MN SUFFIX
CASE 485M
1
52
MARKING DIAGRAM*
52
1
NB3N
121K
AWLYYWWG
•
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333 and
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
400 MHz
340 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
100 ps Max Within Device Skew
150 ps Max Device−to−Device Skew
Dtpd
100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
0.1 ps Typical RMS Additive Phase Jitter
LVDS Output Levels Optional with Interface Termination
Operating Range: V
CC
= 3.0 V to 3.6 V with GND = 0 V
Typical HCSL Output Level (700 mV Peak−to−Peak)
These are Pb−Free Devices
Clock Distribution
PCIe I, II, III
Networking
High End Computing
Routers
A
WL
YY
WW
G
= Assembly Site
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
Q0
VTCLK
Q0
Q1
Q1
CLK
CLK
Q19
Q19
Applications
VTCLK
V
CC
GND
IREF
R
REF
Q20
Q20
Figure 1. Simplified Logic Diagram
ORDERING INFORMATION
End Products
•
Servers
•
FBDIMM Memory Card
©
Semiconductor Components Industries, LLC, 2012
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
March, 2012
−
Rev. 1
1
Publication Order Number:
NB3N121K/D
NB3N121K
VCC
Q0
Q0
Q1
Q1
Q2
Q2
Q3
Q3
Q4
Q4
Q5
Q5
Exposed Pad (EP)
52
51
50
49
48
47
46
45
44
43
42
41
40
IREF
GND
VTCLK
CLK
CLK
VTCLK
V
CC
Q20
Q20
Q19
Q19
Q18
Q18
1
2
3
4
5
6
7
8
9
10
11
12
13
39
38
37
36
35
34
VCC
Q6
Q6
Q7
Q7
Q8
Q8
Q9
Q9
Q10
Q10
Q11
Q11
NB3N121K
33
32
31
30
29
28
27
14
15
16
17
18
19
20
21
22
23
24
25
Q12
Q17
Q17
Q16
Q16
Q15
Q15
Q14
Q14
Q13
Q13
Q12
Figure 2. Pinout Configuration
(Top View)
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2
VCC
26
NB3N121K
Table 1. PIN DESCRIPTION
Pin
1
Name
IREF
I/O
Output
Description
Use the IREF pin to set the output drive. Connect a 475
W
RREF resist-
or from the IREF pin to GND to produce 2.63 mA of IREF current. A
current mirror multiplies IREF by a factor of 5.4 to force 14.2 mA through
a 50
W
output load. See Figures 6 and 12. Minimize capacitance.
Supply Ground. GND pin must be externally connected to power supply
to guarantee proper operation.
Internal 50
W
Termination Resistor connection Pins. In the differential
configuration when the input termination pins are connected to the com-
mon termination voltage, and if no signal is applied then the device may
be susceptible to self−oscillation.
Clock (TRUE) Input
2
3, 6
GND
VTCLK,
VTCLK
−
−
4
CLK
LVPECL,
HCSL,
LVCMOS or
LVTTL Input
LVPECL,
HCSL,
LVCMOS or
LVTTL Input
−
5
CLK
Clock (INVERT) Input
7, 26, 39, 52
8, 10, 12, 14, 16, 18, 20, 22,
24, 27, 29, 31, 33, 35, 37,
40,42, 44, 46, 48, 50
9, 11, 13, 15, 17, 19, 21, 23,
25, 28, 30, 32, 34, 36, 38,
41, 43, 45, 47, 49, 51
Exposed Pad
VCC
Q[20−0]
Positive Supply pins. VCC pins must be externally connected to a power
supply to guarantee proper operation.
HCSL or LVDS Output (INVERT) (Note 1)
(Note 1) Output
HCSL or LVDS Output (TRUE) (Note 1)
(Note 1) Output
GND
Exposed Pad. The thermally exposed pad (EP) on package bottom (see
case drawing) must be attached to a sufficient heat−sinking conduit for
proper thermal operation. The pad is electrically connected ot GND and
must be connected to GND on the PC board.
Q[20−0]
EP
1. Outputs can also interface to LVDS receiver when terminated per Figure 11.
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NB3N121K
Table 2. ATTRIBUTES
Characteristic
ESD Protection
Moisture Sensitivity (Note 2)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
2. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
QFN−52
Oxygen Index: 28 to 34
Value
>2 kV
200 V
Level 1
UL 94 V−0 @ 0.125 in
409
Table 3. MAXIMUM RATINGS
(Note 3)
Symbol
V
CC
V
I
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Positive Input
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient) (Note 3)
Thermal Resistance (Junction−to−Case)
Wave Solder
Pb−Free
0 lfpm
500 lfpm
2S2P (Note 4)
QFN−52
QFN−52
QFN−52
Condition 1
GND = 0 V
GND = 0 V
Continuous
Surge
QFN−52
Condition 2
Rating
4.6
GND
−
0.3
≤
V
I
≤
V
CC
50
100
−40
to +85
−65
to +150
25
19.6
21
265
Unit
V
V
mA
mA
°C
°C
°C/W
°C/W
°C/W
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard 51−6, multilayer board
−
2S2P (2 signal, 2 power).
4. JEDEC standard multilayer board
−
2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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4
NB3N121K
Table 4. DC CHARACTERISTICS
(V
CC
= 3.0 V to 3.6 V, T
A
=
−40°C
to +85°C Note 5)
Symbol
I
GND
I
CC
I
IH
I
IL
R
TIN
V
th
V
IH
V
IL
V
IHD
V
ILD
V
ID
V
CMR
V
OH
V
OL
Characteristic
GND Supply Current (All Outputs Loaded)
Power Supply Current (All Outputs Loaded)
Input HIGH Current
Input LOW Current
Internal Input Termination Resistor
−150
45
Min
Typ
120
440
2.0
−2.0
50
55
Max
150
500
150
Unit
mA
mA
mA
mA
W
DIFFERENTIAL INPUT DRIVEN SINGLE*ENDED
(See Figures 4 and 5)
Input Threshold Reference Voltage Range (Note 6)
Single−Ended Input HIGH Voltage
Single−Ended Input LOW Voltage
350
V
th
+ 150
GND
V
CC
−
1000
V
CC
V
th
−
150
V
CC
−
850
V
CC
−
1000
V
CC
−
850
V
CC
−
1000
740
0
900
150
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 7, 8 and 9)
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage (V
IHD
−
V
ILD
)
Input Common Mode Range
425
GND
150
350
mV
mV
mV
mV
HCSL OUTPUTS
(Figure 4)
Output HIGH Voltage
Output LOW Voltage
600
−150
mV
mV
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Measurements taken with with outputs loaded 50
W
to GND. Connect a 475
W
resister from IREF (Pin 1) to GND. See Figure 6.
6. V
th
is applied to the complementary input when operating in single ended mode per Figure 4.
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