HANBit
HMN28D
Non-Volatile SRAM MODULE 16Kbit (2K x 8-Bit), 24pin DIP, 5V
Part No. HMN28D
GENERAL DESCRIPTION
The HMN28D are 16,384-bit, fully static, nonvolatile SRAM’s organized as 2,048 bytes by 8 bits. Each NVSRAM has a
self-contained lithium energy source and control circuitry, which constantly monitors Vcc for an out-of-tolerance condition.
When such a condition occurs, the lithium energy source is automatically switched on and writes protection is
unconditionally enabled to prevent data corruption. The HMN28D devices can be used in place of existing 2K x 8 SRAM’s
directly conforming to the popular byte wide 24-pin DIP standard. There is no limit on the number of write cycles that can
be executed and no additional support circuitry is required for microprocessor interfacing.
The HMN28D uses extremely low standby current CMOS SRAM’s, coupled with small lithium coin cells to provide non-
volatility without long write-cycle times and the write-cycle limitations associated with EEPROM.
FEATURES
w
Access time : 70, 85, 120 and 150ns
w
High-density design : 2KByte Design
w
Battery internally isolated until power is applied
w
JEDEC standard 24-pin DIP Package
w
Low-power CMOS
w
Unlimited writes cycles
w
Data retention in the absence of V
CC
w
10-years minimum data retention in absence of power
w
Automatic write-protection during power-up/power-down
cycles
w
Data is automatically protected during power loss
w
Conventional SRAM operation; unlimited write cycles
PIN ASSIGNMENT
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
Vss
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
A8
A9
/WE
/OE
A10
/CE
DQ7
DQ6
DQ5
DQ4
DQ3
24-pin Encapsulated package
OPTIONS
w
Timing
70 ns
85 ns
120 ns
150 ns
MARKING
-70
-85
-120
-150
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
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HANBit Electronics Co.,Ltd
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FUNCTIONAL DESCRIPTION
HMN28D
The HMN28D executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the
address inputs(A
0
-A
10
) defines which of the 2,048 bytes of data is accessed. Valid data will be available to the eight data
output drivers within t
ACC
(access time) after the last address input signal is stable.
When power is valid, the HMN28D operates as a standard CMOS SRAM. During power-down and power-up cycles, the
HMN28D acts as a nonvolatile memory, automatically protecting and preserving the memory contents.
The HMN28D is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are
stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is
terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE
must return to the high state for a minimum recovery time (t
WR
) before another cycle can be initiated. The /OE control
signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled
(/CE and /OE active) then /WE will disable the outputs in t
ODW
from its falling edge.
The HMN28D provides full functional capability for VCC greater than 4.5 V and write protects by 4.37 V nominal. Power-
down/power-up control circuitry constantly monitors the V
CC
supply for a power-fail-detect threshold V
PFD
. When V
CC
falls
below the V
PFD
threshold, the SRAM automatically write-protects the data. All inputs to the RAM become
“don’t
care” and
all outputs are high impedance. As VCC falls below approximately 3 V, the power switching circuit connects the lithium
energy soure to RAM to retain data. During power-up, when VCC rises above approximately 3.0 volts, the power switching
circuit connects external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after VCC exceeds 4.5 volts.
BLOCK DIAGRAM
A
0
-A
10
DQ
0
-DQ
7
PIN DESCRIPTION
A
0
-A
10
: Address Input
/CE : Chip Enable
V
SS
: Ground
/OE
/WE
2K x 8
SRAM
Block
Power
/CE
CON
V
CC
DQ
0
-DQ
7
: Data In / Data Out
/WE : Write Enable
/CE
Power
–
Fail
Control
Lithium
Cell
/OE : Output Enable
V
CC
: Power (+5V)
NC : No Connection
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TRUTH TABLE
MODE
Not selected
Output disable
Read
Write
/OE
X
H
L
X
/CE
H
L
L
L
/WE
X
H
H
L
I/O OPERATION
High Z
High Z
D
OUT
D
IN
HMN28D
POWER
Standby
Active
Active
Active
ABSOLUTE MAXIMUM RATINGS
PARAMETER
DC voltage applied on V
CC
relative to V
SS
DC Voltage applied on any pin excluding V
CC
relative to V
SS
Operating temperature
Storage temperature
Temperature under bias
Soldering temperature
SYMBOL
V
CC
V
T
T
OPR
T
STG
T
BIAS
T
SOLDER
RATING
-0.3V to 7.0V
-0.3V to 7.0V
0 to 70°C
-40°C to 70°C
-10°C to 70°C
260°C
For 10 second
V
T
≤
V
CC
+0.3
CONDITIONS
NOTE:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded.
Functional operation should be restricted to the Recommended DC Operating Conditions detailed in this data sheet.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
( T
A
= T
OPR
)
PARAMETER
Supply Voltage
Ground
Input high voltage
Input low voltage
SYMBOL
V
CC
V
SS
V
IH
V
IL
MIN
4.5V
0
2.2
-0.3
TYPICAL
5.0V
0
-
-
MAX
5.5V
0
V
CC
+0.3V
0.8V
NOTE:
Typical values indicate operation at T
A
= 25℃
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
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HANBit Electronics Co.,Ltd
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DC ELECTRICAL CHARACTERISTICS
(T
A
= T
OPR
, V
CCmin
£
V
CC
≤
V
CCmax
)
PARAMETER
Input Leakage Current
Output Leakage Current
Output high voltage
Output low voltage
Standby supply current
Standby supply current
CONDITIONS
V
IN
=V
SS
to V
CC
/CE=V
IH
or /OE=V
IH
Or /WE=V
IL
I
OH
=-1.0mA
I
OL
= 2.1mA
/CE=V
IH
/CE≥ V
CC
-0.2V,
0V≤ V
IN
≤
0.2V,
or V
IN
≥
V
CC
-0.2V
Operating supply current
Power-fail-detect voltage
Supply switch-over voltage
Min.cycle,duty=100%,
/CE=V
IL
, I
I/O
=0㎃
I
CC
V
PFD
V
SO
-
4.30
-
65
4.37
3
I
SB1
-
2.5
SYMBOL
I
LI
I
LO
V
OH
V
OL
I
SB
MIN
-
-
2.4
-
-
TYP.
-
-
-
-
4
HMN28D
MAX
±
1
±
1
-
0.4
2
100
UNIT
mA
mA
V
V
㎃
mA
15
4.50
-
㎃
V
V
CAPACITANCE
(T
A
=25℃ , f=1MHz, V
CC
=5.0V)
DESCRIPTION
Input Capacitance
Input/Output Capacitance
CONDITIONS
Input voltage = 0V
Output voltage = 0V
SYMBOL
C
IN
C
I/O
MAX
10
10
MIN
-
-
UNIT
pF
pF
CHARACTERISTICS
(Test Conditions)
PARAMETER
Input pulse levels
Input rise and fall times
Input and output timing
reference levels
Output load
(including scope and jig)
VALUE
0 to 3V
5 ns
1.5V
(unless otherwise specified)
See Figures 1and 2
+5V
D
OUT
1
KΩ
Figure 1.
Output Load A
1.9
KΩ
D
OUT
100㎊
1
KΩ
Figure 2.
Output Load B
+5V
1.9
KΩ
5㎊
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READ CYCLE
(T
A
= T
OPR
, V
CCmin
£
V
CC
≤
V
CCmax
)
PARAMETER
Read Cycle Time
Address Access Time
Chip enable access time
Output enable to Output valid
Chip enable to output in low Z
Output enable to output in low Z
Chip disable to output in high Z
Output disable to output high Z
Output hold from address change
SYMBOL
t
RC
t
ACC
t
ACE
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
Output load A
Output load A
Output load A
Output load B
Output load B
Output load B
Output load B
Output load A
CONDITIONS
MIN
70
-
-
-
5
5
0
0
10
-70
MAX
-
70
70
35
-
-
25
25
-
MIN
85
-
-
-
5
0
0
0
10
-85
MAX
-
85
85
45
-
-
35
25
-
-120
MIN
120
-
-
-
5
0
0
0
10
MAX
-
120
120
60
-
-
45
35
-
HMN28D
-150
MIN
150
-
-
-
10
5
0
0
10
MAX
-
150
150
70
-
-
60
50
-
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE
(T
A
= T
OPR
, V
ccmin
£
V
cc
≤
V
ccmax
)
PARAMETER
Write Cycle Time
Chip enable to end of write
Address setup time
Address valid to end of write
Write pulse width
Write recovery time (write cycle 1)
Write recovery time (write cycle 2)
Data valid to end of write
Data hold time (write cycle 1)
Data hold time (write cycle 2)
Write enabled to output in high Z
Output active from end of write
SYMBOL
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1
t
WR2
t
DW
t
DH1
t
DH2
t
WZ
t
OW
Note 4
Note 4
Note 5
Note 5
Note 1
Note 2
Note 1
Note 1
Note 3
Note 3
CONDITIONS
MIN
70
65
0
65
55
5
15
30
0
10
0
5
-70
MAX
-
-
-
-
-
-
-
-
-
-
25
-
MIN
85
75
0
75
65
5
15
35
0
10
0
0
-85
MAX
-
-
-
-
-
-
-
-
-
-
30
-
-120
MIN
120
100
0
100
85
5
15
45
0
10
0
0
MAX
-
-
-
-
-
-
-
-
-
-
40
-
-150
Min
150
100
0
90
90
5
15
50
0
0
0
5
Max
-
-
-
-
-
-
-
-
-
-
50
-
UNI
T
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTE:
1. A write ends at the earlier transition of /CE going high and /WE going high.
2. A write occurs during the overlap of allow /CE and a low /WE. A write begins at the later transition of /CE
going low and /WE going low.
3. Either t
WR1
or t
WR2
must be met.
4. Either t
DH1
or t
DH2
must be met.
5. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain in high-
impedance state.
URL : www.hbe.co.kr
Rev. 0.0 (April, 2002)
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