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MAY 2003
XRT73L02M
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
GENERAL DESCRIPTION
The XRT73L02M is a two-channel fully integrated
Line Interface Unit (LIU) for E3/DS3/STS-1 applica-
tions. It incorporates independent Receivers, Trans-
mitters in a single 100 pin TQFP package.
The XRT73L02M can be configured to operate in ei-
ther E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1
(51.84 MHz) modes.The transmitter can be turned off
or tri-stated for redundancy support and for conserv-
ing power.
The XRT73L02M’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of ca-
ble attenuation.
The XRT73L02M provides both Serial Microproces-
sor Interface as well as Hardware mode for program-
ming and control.
The XRT73L02M supports local,remote and digital
loop-backs. The XRT73L02M also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
•
Provides low jitter clock outputs for either DS3,E3
or STS-1 rates.
•
On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
•
Provides low jitter output clock.
TRANSMITTER:
•
Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
•
Tri-state Transmit output capability for redundancy
applications
•
Transmitter can be turned on or off.
CONTROL AND DIAGNOSTICS:
•
5 wire Serial Microprocessor Interface for control
and configuration.
•
Supports optional internal Transmit Driver Monitor-
ing.
•
PRBS error counter register to accumulate errors.
•
Hardware Mode for control and configuration.
•
Supports Local, Remote and Digital Loop-backs.
•
Single 3.3 V ± 5% power supply.
•
5 V Tolerant I/O.
•
Available in 100 pin TQFP.
•
-40°C to 85°C Industrial Temperature Range.
FEATURES
RECEIVER:
•
On chip Clock and Data Recovery circuit for high
input jitter tolerance.
•
Meets the jitter tolerance requirements as specified
in ITU-T G.823_1993 for E3 and Telcordia GR-499-
CORE for DS3 applications.
•
Detects and Clears LOS as per G.775.
•
Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
•
On chip B3ZS/HDB3 encoder and decoder that can
either be enabled or disabled.
•
On-chip clock synthesizer generates the appropri-
ate rate clock from a single frequency XTAL.
APPLICATIONS
•
E3/DS3 Access Equipment.
•
STS1-SPE to DS3 Mapper.
•
DSLAMs.
•
Digital Cross Connect Systems.
•
CSU/DSU Equipment.
•
Routers.
•
Fiber Optic Terminals.
Exar
Corporation 48720 Kato Road, Fremont CA, 94538
•
(510) 668-7000
•
FAX (510) 668-7017
•
www.exar.com
XRT73L02M
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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F
IGURE
1. B
LOCK
D
IAGRAM OF THE
XRT 73L02M
SDI
SDO
INT
SClk
CS
RESET
HOST/HW
STS-1/DS3
E3
REQEN
RTIP
RRING
SR/DR
LLB
XRT75L03
Serial
Processor
Interface
CLK_OUT
E3Clk,DS3Clk,
STS-1Clk
RLOL
RxON
RxClkINV
Peak Detector
AGC/
Equalizer
Slicer
Clock & Data
Recovery
LOS
Detector
Clock
Synthesizer
Invert
HDB3/
B3ZS
Decoder
RxClk
RPOS
RNEG/
LCV
MUX
Local
LoopBack
Remote
LoopBack
RLB
RLOS
HDB3/
B3ZS
Encoder
TPOS
TNEG
TxClk
TAOS
TxLEV
TxON
TTIP
TRING
MTIP
MRING
DMO
Line
Driver
Tx
Pulse
Shaping
Tx
Control
Timing
Control
MUX
Device
Monitor
Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.
TRANSMIT INTERFACE CHARACTERISTICS
•
Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
to the line
•
Integrated Pulse Shaping Circuit.
•
Built-in B3ZS/HDB3 Encoder (which can be dis-
abled).
•
Accepts Transmit Clock with duty cycle of 30%-
70%.
•
Generates pulses that comply with the ITU-T G.703
pulse template for E3 applications.
•
Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499
-CORE
and ANSI T1.102_1993.
•
Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE.
•
Transmitter can be turned off in order to support
redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
•
Integrated Adaptive Receive Equalization for opti-
mal Clock and Data Recovery.
•
Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications.
•
Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications.
•
Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications.
•
Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms.
•
Built-in B3ZS/HDB3 Decoder (which can be dis-
abled).
•
Recovered Data can be muted while the LOS Con-
dition is declared.
•
Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment.
2
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TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
XRT73L02M
REV. 1.0.0
F
IGURE
2. P
IN
O
UT OF THE
XRT73L02M
TNEG_0
TPOS_0
TxCLK_0
DMO_0
CLKOUT_0
TxON
TxMON
TxAGND_0
TxAVDD_0
AGND_0
AVDD_0
DVDD_0
DGND_0
RxDVDD_0
RxDGND_0
RxCLK_0
RPOS_0
RNEG/LCV_0
RLOS_0
RLOL_0
TEST
RESET
ICT
SFM_EN
SR/DR
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
TAOS_0
TxLEV_0
MRING_0
MTIP_0
TRING_0
TTIP_0
TxDVDD_0
TxDGND_0
DVDD
E3CLK
DGND
DGND
DS3CLK
DVDD
DVDD
STS1CLK/SFMCLK
DGND
TxDGND_1
TxDVDD_1
TTIP_1
TRING_1
MTIP_1
MRING_1
TxLEV_1
TAOS_1
XRT73L02M
TNEG_1
TPOS_1
TxCLK_1
DMO_1
CLKOUT_1
CLKOUT_EN
TxAGND_1
TxAVDD_1
AGND_1
AVDD_1
DVDD_1
DGND_1
DVDD_1
DGND_1
RxCLK_1
RPOS_1
RNEG/LCV_1
RLOS_1
RLOL_1
SDI/RxON
SCLK/TxCLKINV
CS/RxCLKINV
INT/LOSMUT
SDO/RxMON
HOST/HW
P
ART
N
UMBER
XRT73L02MIV
REQEN_0
E3_0
STS1/DS3_0
LLB_0
RLB_0
RxAVDD_0
RxAGND_0
RRING_0
RTIP_0
AGND
RxA
RxB
AVDD
AGND
AGND
AGND
RTIP_1
RRING_1
RxAGND_1
RxAVDD_1
RLB_1
LLB_1
STS1/DS3_1
E3_1
REQEN_1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
ORDERING INFORMATION
P
ACKAGE
14mm x 14mm 100 Pin TQFP
O
PERATING
T
EMPERATURE
R
ANGE
-40
°
C to +85
°
C
3
XRT73L02M
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
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TABLE OF CONTENTS
GENERAL DESCRIPTION ............................................................................................... 1
F
EATURES
.................................................................................................................................................... 1
A
PPLICATIONS
.............................................................................................................................................. 1
Figure 1. Block Diagram of the XRT73L02M ..................................................................................................... 2
T
RANSMIT
I
NTERFACE
C
HARACTERISTICS
...................................................................................................... 2
R
ECEIVE
I
NTERFACE
C
HARACTERISTICS
........................................................................................................ 2
Figure 2. Pin Out of the XRT73L02M ................................................................................................................ 3
ORDERING INFORMATION ................................................................................................................... 3
TABLE OF CONTENTS .................................................................................................................................... I
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................ 4
T
RANSMIT
I
NTERFACE
................................................................................................................................... 4
R
ECEIVE
I
NTERFACE
..................................................................................................................................... 6
C
LOCK
I
NTERFACE
........................................................................................................................................ 9
O
PERATING
M
ODE
S
ELEC
T ......................................................................................................................... 10
C
ONTROL AND
A
LARM
I
NTERFACE
............................................................................................................... 14
A
NALOG
P
OWER AND
G
ROUND
................................................................................................................... 15
DIGITAL
P
OWER AND
G
ROUND
..................................................................................................................... 16
1.0 ELECTRICAL CHARACTERISTICS ................................................................................................. 17
T
ABLE
1: A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................ 17
T
ABLE
2: DC E
LECTRICAL
C
HARACTERISTICS
: ................................................................................................... 17
2.0 TIMING CHARACTERISTICS ............................................................................................................ 18
Figure 3. Typical interface between terminal equipment and the XRT73L02M (dual-rail data) ...................... 18
Figure 4. Transmitter Terminal Input Timing ................................................................................................... 18
Figure 5. Receiver Data output and code violation timing .............................................................................. 19
Figure 6. Transmit Pulse Amplitude test circuit for E3, DS3 and STS-1 Rates ............................................... 20
3.0 LINE SIDE CHARACTERISTICS: ..................................................................................................... 20
3.1 E3
LINE SIDE PARAMETERS
: ............................................................................................................................. 20
Figure 7. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 .....................................................
T
ABLE
3: E3 T
RANSMITTER LINE SIDE OUTPUT AND RECEIVER LINE SIDE INPUT SPECIFICATIONS
...........................
Figure 8. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ............
T
ABLE
4: STS-1 P
ULSE
M
ASK
E
QUATIONS
........................................................................................................
T
ABLE
5: STS-1 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-253) .
Figure 9. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 ..................................................
T
ABLE
6: DS3 P
ULSE
M
ASK
E
QUATIONS
...........................................................................................................
T
ABLE
7: DS3 T
RANSMITTER
L
INE
S
IDE
O
UTPUT AND
R
ECEIVER
L
INE
S
IDE
I
NPUT
S
PECIFICATIONS
(GR-499) .....
Figure 10. Microprocessor Serial Interface Structure ......................................................................................
Figure 11. Timing Diagram for the Microprocessor Serial Interface ................................................................
T
ABLE
8: M
ICROPROCESSOR
S
ERIAL
I
NTERFACE
T
IMINGS
( TA = 250C, VDD=3.3V± 5%
AND LOAD
= 10
P
F) .....
20
21
22
22
23
23
24
24
25
25
26
FUNCTIONAL DESCRIPTION: ........................................................................................ 27
4.0 The Transmitter Section: ................................................................................................................. 27
Figure 12. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 27
Figure 13. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 27
4.0.1 Transmit Clock: .................................................................................................................................. 28
4.0.2 B3ZS/HDB3 Encoder: ......................................................................................................................... 28
Figure 14. B3ZS Encoding Format ................................................................................................................. 28
4.0.3 Transmit Pulse Shaper: ..................................................................................................................... 29
Figure 15. HDB3 Encoding Format ................................................................................................................. 29
4.0.4 Transmit Drive Monitor: ..................................................................................................................... 30
4.0.5 Transmitter Section On/Off: .............................................................................................................. 30
Figure 16. Transmit Driver Monitor set-up. ..................................................................................................... 30
5.0 The Receiver Section: ...................................................................................................................... 31
5.0.1 AGC/Equalizer: ................................................................................................................................... 31
IV
xr
XRT73L02M
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
Figure 17. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 32
Figure 18. Interference Margin Test Set up for E3. ........................................................................................ 32
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
.............................................................................................. 32
5.0.2 Clock and Data Recovery: ................................................................................................................. 33
5.0.3 B3ZS/HDB3 Decoder: ........................................................................................................................ 33
5.0.4 LOS (Loss of Signal) Detector: ......................................................................................................... 34
D
ISABLING
ALOS/DLOS D
ETECTION
: .........................................................................................................
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION AND
C
LEARANCE
T
HRESHOLDS FOR A GIVEN SETTING OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
) ...................................................................
Figure 19. Loss Of Signal Definition for E3 as per ITU-T G.775 ....................................................................
Figure 20. Loss of Signal Definition for E3 as per ITU-T G.775. ....................................................................
6.0 Jitter: .................................................................................................................................................
34
34
35
35
36
6.0.1 Jitter Tolerance - Receiver: ............................................................................................................... 36
Figure 21. Jitter Tolerance Measurements ..................................................................................................... 36
Figure 22. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 37
Figure 23. Input Jitter Tolerance for E3 ......................................................................................................... 37
6.0.2 Jitter Transfer - Receiver/Transmitter: ............................................................................................. 38
T
ABLE
11: J
ITTER
A
MPLITUDE VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) .....................................
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
...............................................................................
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
.......................................................................................................
Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance ..................................................
7.0 Serial Host interface: .......................................................................................................................
T
ABLE
14: F
UNCTIONS OF SHARED PINS
............................................................................................................
T
ABLE
15: R
EGISTER
M
AP AND
B
IT
N
AMES
.......................................................................................................
T
ABLE
16: R
EGISTER
M
AP
D
ESCRIPTION
- G
LOBAL
............................................................................................
T
ABLE
17: R
EGISTER
M
AP AND
B
IT
N
AMES
- C
HANNEL
0 R
EGISTERS
.................................................................
T
ABLE
18: R
EGISTER
M
AP AND
B
IT
N
AMES
- C
HANNEL
1 R
EGISTERS
.................................................................
T
ABLE
20: R
EGISTER
M
AP
D
ESCRIPTION
...........................................................................................................
8.0 Diagnostic Features: ........................................................................................................................
38
38
39
39
40
40
40
41
42
42
43
47
6.1.1 Jitter Generation: ............................................................................................................................... 40
8.1 PRBS G
ENERATOR AND
D
ETECTOR
: ................................................................................................................ 47
8.2 LOOPBACKS: ............................................................................................................................................... 48
8.2.1 ANALOG LOOPBACK: ....................................................................................................................... 48
Figure 25. PRBS MODE ................................................................................................................................. 48
8.2.2 DIGITAL LOOPBACK: ........................................................................................................................ 49
Figure 26. Analog Loopback ........................................................................................................................... 49
8.2.3 REMOTE LOOPBACK: ....................................................................................................................... 50
Figure 27. Digital Loopback ............................................................................................................................ 50
8.3 TRANSMIT ALL ONES (TAOS): ................................................................................................................... 51
Figure 28. Remote Loopback ......................................................................................................................... 51
Figure 29. Transmit All Ones (TAOS) ............................................................................................................. 51
APPENDIX ......................................................................................................................... 52
Figure 30. EVALUATION BOARD SCHEMATICS ......................................................................................... 52
Figure 31. Evaluation Board Schematics ....................................................................................................... 53
ORDERING INFORMATION ................................................................................................................ 54
P
ACKAGE
D
IMENSIONS
- 14
X
20
MM
, 100
PIN PACKAGE
................................................................................ 54
R
EVISIONS
................................................................................................................................................. 55
V
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