P5C060-55 datasheet, PDF - EEWORLD Datasheet

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P5C060-55: Description16 MACROCELL CMOS PLD; CategoryProgrammable logic devices Programmable logic; File Size1006KB，18 Pages; ManufacturerIntel; Websitehttp://www.intel.com/

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P5C060-55 Overview

16 MACROCELL CMOS PLD

P5C060-55 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	DIP
package instruction	DIP, DIP24,.3
Contacts	24
Reach Compliance Code	compliant
Other features	PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS
Architecture	PAL-TYPE
maximum clock frequency	14.28 MHz
JESD-30 code	R-PDIP-T24
JESD-609 code	e0
length	31.61 mm
Dedicated input times	4
Number of I/O lines	16
Number of entries	20
Output times	16
Number of product terms	160
Number of terminals	24
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4 DEDICATED INPUTS, 16 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP24,.3
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Programmable logic type	OT PLD
propagation delay	55 ns
Certification status	Not Qualified
Maximum seat height	4.32 mm
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	7.62 mm
Base Number Matches	1

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P5C060-55 Related Products

	P5C060-55	5C060	D5C060-55	D5C060-45	N5C060-45	N5C060-55	P5C060-45	TD5C060-45	TN5C060-45
Description	16 MACROCELL CMOS PLD	16 MACROCELL CMOS PLD	16 MACROCELL CMOS PLD	16 MACROCELL CMOS PLD	16 MACROCELL CMOS PLD	16 MACROCELL CMOS PLD	16 MACROCELL CMOS PLD	16 MACROCELL CMOS PLD	16 MACROCELL CMOS PLD
Is it Rohs certified?	incompatible	-	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible	incompatible
Parts packaging code	DIP	-	DIP	DIP	QLCC	QLCC	DIP	-	-
package instruction	DIP, DIP24,.3	-	WDIP, DIP24,.3	WDIP, DIP24,.3	QCCJ, LDCC28,.5SQ	QCCJ, LDCC28,.5SQ	DIP, DIP24,.3	DIP, DIP24,.3	QCCJ, LDCC28,.5SQ
Contacts	24	-	24	24	28	28	24	-	-
Reach Compliance Code	compliant	-	compliant	compliant	compli	compli	compliant	compliant	compli
Other features	PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	-	PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	PAL WITH MACROCELLS; 16 MACROCELLS; 2 EXTERNAL CLOCKS; ASYNCHRONOUS CLOCKS	-	-
Architecture	PAL-TYPE	-	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE	PAL-TYPE
maximum clock frequency	14.28 MHz	-	14.28 MHz	16.13 MHz	16.13 MHz	14.28 MHz	16.13 MHz	22 MHz	22 MHz
JESD-30 code	R-PDIP-T24	-	R-GDIP-T24	R-GDIP-T24	S-PQCC-J28	S-PQCC-J28	R-PDIP-T24	R-XDIP-T24	S-PQCC-J28
JESD-609 code	e0	-	e0	e0	e0	e0	e0	e0	e0
length	31.61 mm	-	32.07 mm	32.07 mm	11.5062 mm	11.5062 mm	31.61 mm	-	-
Dedicated input times	4	-	4	4	4	4	4	-	-
Number of I/O lines	16	-	16	16	16	16	16	-	-
Number of entries	20	-	20	20	20	20	20	20	20
Output times	16	-	16	16	16	16	16	16	16
Number of product terms	160	-	160	160	160	160	160	160	160
Number of terminals	24	-	24	24	28	28	24	24	28
Maximum operating temperature	70 °C	-	70 °C	70 °C	70 °C	70 °C	70 °C	85 °C	85 °C
organize	4 DEDICATED INPUTS, 16 I/O	-	4 DEDICATED INPUTS, 16 I/O	4 DEDICATED INPUTS, 16 I/O	4 DEDICATED INPUTS, 16 I/O	4 DEDICATED INPUTS, 16 I/O	4 DEDICATED INPUTS, 16 I/O	-	-
Output function	MACROCELL	-	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL	MACROCELL
Package body material	PLASTIC/EPOXY	-	CERAMIC, GLASS-SEALED	CERAMIC, GLASS-SEALED	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	CERAMIC	PLASTIC/EPOXY
encapsulated code	DIP	-	WDIP	WDIP	QCCJ	QCCJ	DIP	DIP	QCCJ
Encapsulate equivalent code	DIP24,.3	-	DIP24,.3	DIP24,.3	LDCC28,.5SQ	LDCC28,.5SQ	DIP24,.3	DIP24,.3	LDCC28,.5SQ
Package shape	RECTANGULAR	-	RECTANGULAR	RECTANGULAR	SQUARE	SQUARE	RECTANGULAR	RECTANGULAR	SQUARE
Package form	IN-LINE	-	IN-LINE, WINDOW	IN-LINE, WINDOW	CHIP CARRIER	CHIP CARRIER	IN-LINE	IN-LINE	CHIP CARRIER
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
power supply	5 V	-	5 V	5 V	5 V	5 V	5 V	5 V	5 V
Programmable logic type	OT PLD	-	UV PLD	UV PLD	OT PLD	OT PLD	OT PLD	EE PLD	EE PLD
propagation delay	55 ns	-	55 ns	45 ns	45 ns	55 ns	45 ns	-	-
Certification status	Not Qualified	-	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.32 mm	-	5.72 mm	5.72 mm	4.57 mm	4.57 mm	4.32 mm	-	-
Maximum supply voltage	5.25 V	-	5.25 V	5.25 V	5.25 V	5.25 V	5.25 V	-	-
Minimum supply voltage	4.75 V	-	4.75 V	4.75 V	4.75 V	4.75 V	4.75 V	-	-
Nominal supply voltage	5 V	-	5 V	5 V	5 V	5 V	5 V	5 V	5 V
surface mount	NO	-	NO	NO	YES	YES	NO	NO	YES
technology	CMOS	-	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	-	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL	INDUSTRIAL	INDUSTRIAL
Terminal surface	Tin/Lead (Sn/Pb)	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE	-	THROUGH-HOLE	THROUGH-HOLE	J BEND	J BEND	THROUGH-HOLE	THROUGH-HOLE	J BEND
Terminal pitch	2.54 mm	-	2.54 mm	2.54 mm	1.27 mm	1.27 mm	2.54 mm	2.54 mm	1.27 mm
Terminal location	DUAL	-	DUAL	DUAL	QUAD	QUAD	DUAL	DUAL	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED	-	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	NOT SPECIFIED	-
width	7.62 mm	-	7.62 mm	7.62 mm	11.5062 mm	11.5062 mm	7.62 mm	-	-
Base Number Matches	1	-	1	1	-	-	1	1	1

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