240-pin, dual in-line very low profile (VLP) memory
module
Fast data transfer rates: PC2-6400*, PC2-5300*,
PC2-4300 and PC2-3200
Utilizes 800, 667, 533 and 400 Mb/s DDR2 SDRAM
components
V
CC
= V
CCQ
= 1.8V
V
CCSPD
= +1.7V to +3.6V
Differential data strobe (DQS, DQS#) option
Four-bit prefetch architecture
DLL to align DQ and DQS transitions with CK
Multiple internal device banks for concurrent
operation
Supports duplicate output strobe (RDQS/RDQS#)
Programmable CAS# latency (CL): 3, 4, 5 and 6
Adjustable data-output drive strength
On-die termination (ODT)
Posted CAS# additive latency: 0, 1, 2, 3 and 4
Serial Presence Detect (SPD) with EEPROM
64ms: 8,192 cycle refresh
Gold edge contacts
ECC error detection and correction
Dual Rank
RoHS compliant
Package option
• 240 Pin VLP: 18.29mm (0.720") TYP
DESCRIPTION
The W3HG2128M72ACER is a 2x128Mx72 Double Data
Rate DDR2 SDRAM high density module based on DDR2
SDRAM components. This memory module consists
of eighteen stacks of 256Mx4 bit with 4 banks DDR2
Synchronous DRAMs in FBGA packages, mounted on a
240-pin DIMM FR4 substrate.
* This product is under development, is not qualified or characterized and is subject to
change without notice.
NOTE: Consult factory for availability of:
• Vendor source control options
• Industrial temperature option
• Parity function
OPERATING FREQUENCIES
PC2-3200
Clock Speed
CL-t
RCD
-t
RP
* Consult factory for availability
PC2-4300
266MHz
4-4-4
PC2-5300*
333MHz
5-5-5
PC2-6400*
400MHz
6-6-6
200MHz
3-3-3
May 2006
Rev. 5
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
PIN CONFIGURATION
Pin No.
Symbol
Pin No.
1
V
REF
61
2
V
SS
62
3
DQ0
63
4
DQ1
64
5
V
SS
65
6
DQS0#
66
7
DQS0
67
8
V
SS
68
9
DQ2
69
10
DQ3
70
71
11
V
SS
12
DQ8
72
13
DQ9
73
14
V
SS
74
15
DQS1#
75
16
DQS1
76
77
17
V
SS
18
RESET#
78
19
NC
79
20
V
SS
80
21
DQ10
81
22
DQ11
82
83
23
V
SS
24
DQ16
84
25
DQ17
85
86
26
V
SS
27
DQS2#
87
28
DQS2
88
89
29
V
SS
30
DQ18
90
31
DQ19
91
32
V
SS
92
33
DQ24
93
34
DQ25
94
95
35
V
SS
36
DQS3#
96
37
DQS3
97
38
V
SS
98
39
DQ26
99
40
DQ27
100
101
41
V
SS
42
CB0
102
43
CB1
103
44
V
SS
104
45
DQS8#
105
46
DQS8
106
107
47
V
SS
48
CB2
108
49
CB3
109
50
V
SS
110
51
V
CCQ
111
52
CKE0
112
113
53
V
CC
54
NC
114
55
NC/ERR_OUT
115
56
V
CCQ
116
57
A11
117
58
A7
118
119
59
V
CC
60
A5
120
May 2006
Rev. 5
Symbol
A4
V
CCQ
A2
V
CC
V
SS
V
SS
V
CC
NC/PAR_IN
V
CC
A10/AP
BA0
V
CCQ
WE#
CAS#
V
CCQ
S1#
ODT1
V
CCQ
V
SS
DQ32
DQ33
V
SS
DQS4#
DQS4
V
SS
DQ34
DQ35
V
SS
DQ40
DQ41
V
SS
DQS5#
DQS5
V
SS
DQ42
DQ43
V
SS
DQ48
DQ49
V
SS
SA2
NC
V
SS
DQS6#
DQS6
V
SS
DQ50
DQ51
V
SS
DQ56
DQ57
V
SS
DQS7#
DQS7
V
SS
DQ58
DQ59
V
SS
SDA
SCL
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
Symbol
V
SS
DQ4
DQ5
V
SS
DQS9
DQS9#
V
SS
DQ6
DQ7
V
SS
DQ12
DQ13
V
SS
DQS10
DQS10#
V
SS
NC
NC
V
SS
DQ14
DQ15
V
SS
DQ20
DQ21
V
SS
DQS11
DQS11#
V
SS
DQ22
DQ23
V
SS
DQ28
DQ29
V
SS
DQS12
DQS12#
V
SS
DQ30
DQ31
V
SS
CB4
CB5
V
SS
DQS17
DQS17#
V
SS
CB6
CB7
V
SS
V
CCQ
CKE1
V
CC
NC
NC
V
CCQ
A12
A9
V
CC
A8
A6
Pin No.
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
Symbol
V
CCQ
A3
A1
V
CC
CK0
CK0#
V
CC
A0
V
CC
BA1
V
CCQ
RAS#
S0#
V
CCQ
ODT0
A13
V
CC
V
SS
DQ36
DQ37
V
SS
DQS13
NC/DQS13#
V
SS
DQ38
DQ39
V
SS
DQ44
DQ45
V
SS
DQS14
NC/DQS14#
V
SS
DQ46
DQ47
V
SS
DQ52
DQ53
V
SS
NC
NC
V
SS
DQS15
NC/DQS15#
V
SS
DQ54
DQ55
V
SS
DQ60
DQ61
V
SS
DQS16
NC/DQS16#
V
SS
DQ62
DQ63
V
SS
V
CC
SPD
SA0
SA1
2
W3HG2128M72ACER-AD6
PRELIMINARY
PIN NAMES
Pin Name
A0-A13
BA0,BA1
DQ0-DQ63
CB0-CB7
DQS0-DQS8
DQS0#-DQS8#
DM0-DM8
DQS9#-DQS17#
DQS9-DQS17
ODT0, ODT1
CK0,CK0#
CKE0, CKE1
S0#, S1#
RAS#
CAS#
WE#
RESET#
SA0-SA2
SDA
SCL
V
CC
V
CCQ
V
SS
V
REF
V
CC
SPD
NC
Function
Address Inputs
SDRAM Bank Address
Data Input/Output
Check Bits
Data strobes
Data strobes complement
Data Masks
Data Strobe Negative
Data Strobe
On-die termination control
Clock Inputs, positive line
Clock Enables
Chip Selects
Row Address Strobe
Column Address Strobe
Write Enable
Register Reset Input
SPD address
SPD Data Input/Output
Serial Presence Detect(SPD) Clock Input
Core Power (1.8V)
I/O Power (1.8V)
Ground
Power Supply for Reference
SPD Power
Spare pins, No connect
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3HG2128M72ACER-AD6
PRELIMINARY
FUNCTIONAL BLOCK DIAGRAM
VSS
RS1#
RS0#
DQS0
DQS0#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQS9
DQS9#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ0
DQ1
DQ2
DQ3
DQS1
DQS1#
DQ8
DQ9
DQ10
DQ11
DQS2
DQS2#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ4
DQ5
DQ6
DQ7
DQS10
DQS10#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ12
DQ13
DQ14
DQ15
DQS11
DQS11#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ16
DQ17
DQ18
DQ19
DQS3
DQS3#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ20
DQ21
DQ22
DQ23
DQS12
DQS12#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ24
DQ25
DQ26
DQ27
DQS4
DQS4#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ28
DQ29
DQ30
DQ31
DQS13
DQS13#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ32
DQ33
DQ34
DQ35
DQS5
DQS5#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ36
DQ37
DQ38
DQ39
DQS14
DQS14#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ40
DQ41
DQ42
DQ43
DQS6
DQS6#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ44
DQ45
DQ46
DQ47
DQS15
DQS15#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ48
DQ49
DQ50
DQ51
DQS#7
DQS7#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ52
DQ53
DQ54
DQ55
DQS16
DQS16#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DQ56
DQ57
DQ58
DQ59
DQS8
DQS8#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DQ60
DQ61
DQ62
DQ63
DQS17
DQS17#
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
DM
CS# DQS DQS#
CB0
CB1
CB2
CB3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
CB4
CB5
CB6
CB7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
V
CCSPD
S0#
S1#
BA0-BA1
A0-A13
RAS#
CAS#
WE#
CKE0
CKE1
ODT0
ODT1
RESET#
PCK7**
PCK7#**
Serial PD
DDR2 SDRAMs
DDR2 SDRAMs
DDR2 SDRAMs
1:2
R
E
G
I
S
T
E
R
RS0#
CS# : DDR2 SDRAMs
RS1#
CS# : DDR2 SDRAMs
RBA0-RBA1
BA0-BA1 : DDR2 SDRAMs
RA0-RA13
A0-A13 : DDR2 SDRAMs
RRAS#
RAS# : DDR2 SDRAMs
RCAS#
CAS# : DDR2 SDRAMs
RWE#
WE# : DDR2 SDRAMs
SCL
RCKE0
CKE : DDR2 SDRAMs
RCKE1
CKE : DDR2 SDRAMs
ODT : DDR2 SDRAMs
RODT0
RODT1
ODT : DDR2 SDRAMs
V
CC
/V
CCQ
V
REF
Serial PD
V
SS
SDA
WP A0
A1
A2
SA0 SA1 SA2
RST#
CK0
CK0#
RESET#**
P
L
L
OE
PCK0-PCK6, PCK8, PCK9
CK : DDR2 SDRAMs
CK# : DDR2 SDRAMs
PCK0#-PCK6#, PCK8#, PCK9#
PCK7
CK : Register
PCK7#
CK# : Register
NOTE: All resistor values are 22 ohms unless otherwise specified.
May 2006
Rev. 5
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
All Voltages Referenced to V
SS
W3HG2128M72ACER-AD6
PRELIMINARY
RECOMMENDED DC OPERATING CONDITIONS
Rating
Parameter
Supply Voltage
Supply Voltage for DLL
Supply Voltage for Output
Input Reference Voltage
Termination Voltage
Symbol
V
CC
V
CCL
V
CCQ
V
REF
V
TT
Min.
1.7
1.7
1.7
0.49*V
CCQ
V
REF
-0.04
Type
1.8
1.8
1.8
0.50*V
CCQ
V
REF
Max.
1.9
1.9
1.9
0.51*V
CCQ
V
REF
+0.04
Units
V
V
V
V
V
Notes
4
4
4
1, 2
3
There is no specific device V
CC
supply voltage requirement for SSTL-1.8 compliance. However under all conditions V
CCQ
must be less than or equal to V
CC
.
1. The value of V
REF
may be selected by the user to provide optimum noise margin in the system. Typically the value of V
REF
is expected to be about 0.5 x V
CCQ
of the transmitting
device and V
REF
is expected to track variations in V
CCQ
.
2. Peak to peak AC noise on V
REF
may not exceed ±2% V
REF
(DC).
3. V
TT
of transmitting device must track V
REF
of receiving device.
4. V
CC
, V
CCQ
and V
CC
L are tied together on this module.
ABSOLUTE MAXIMUM RATINGS
SSTL_1.8V
Symbol
V
CC
V
CCQ
V
CCL
V
IN
, V
OUT
T
STG
Parameter
Voltage on V
CC
pin relative to V
SS
Voltage on V
CCQ
pin relative to V
SS
Voltage on V
CCL
pin relative to V
SS
Voltage on any pin relative to V
SS
Storage Temperature
Rating
- 1.0 V - 2.3 V
- 0.5 V - 2.3 V
- 0.5 V - 2.3 V
- 0.5 V - 2.3 V
-55 to +100
Units
V
V
V
V
C
Notes
5
5
5
5
5, 6
5. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
6. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2 standard.
CAPACITANCE
T
A
= 25°C, f = V
REF
= Gnd, f = 100MHz, V
CC
= V
CCQ
= 1.8V
Parameter
Input Capacitance: CK, CK#
Input Capacitance: CKE, CS#
Input Capacitance: Addr. RAS#, CAS#, WE#, ODT
Input/Output Capacitance: DQ, DQS, DM, DQS#, CB
Symbol
C
CK
CI
1
CI
2
CI
O
Max
5.6
12.4
12.4
15.6
Units
pF
pF
pF
pF
May 2006
Rev. 5
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
W3HG2128M72ACER-AD6
PRELIMINARY
DDR2 I
CC
SPECIFICATIONS AND CONDITIONS
Includes DDR2 SDRAM components only
Symbol Proposed Conditions
I
CC0
Operating one bank active-precharge current;
t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS
min(I
CC
); CKE is HIGH, CS# is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
Operating one bank active-read-precharge current;
I
OUT
= 0mA; BL = 4, CL = CL(I
CC
), AL = 0; t
CK
= t
CK
(I
CC
), t
RC
= t
RC
(I
CC
), t
RAS
= t
RAS
min(I
CC
), t
RCD
=
t
RCD
(I
CC
); CKE is HIGH, CS# is HIGH between valid commands; Address bus inputs are SWITCHING;
Data pattern is same as I
CC4W
Precharge power-down current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control and address bus inputs are STABLE; Data
bus inputs are FLOATING
Precharge quiet standby current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
STABLE; Data bus inputs are FLOATING
Precharge standby current;
All banks idle; t
CK
= t
CK
(I
CC
); CKE is HIGH, CS# is HIGH; Other control and address bus inputs are
SWITCHING; Data bus inputs are SWITCHING
Active power-down current;
All banks open; t
CK
= t
CK
(I
CC
); CKE is LOW; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
Fast PDN Exit MRS(12) = 0
Slow PDN Exit MRS(12) = 1
806
TBD
665
1,720
534
1,530
403
1,530
Units
mA
I
CC1
TBD
1,980
1,800
1,710
mA
I
CC2P
TBD
180
180
180
mA
I
CC2Q
TBD
1,800
1,440
1,260
mA
I
CC2N
TBD
1,980
1,260
360
1,620
1,080
360
1,440
900
360
mA
mA
mA
TBD
TBD
I
CC3P
I
CC3N
Active standby current;
All banks open; t
CK
= t
CK
(I
CC
), t
RAS
= t
RAS
max(I
CC
), t
RP
= t
RP
(I
CC
); CKE is HIGH, CS# is HIGH between
valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
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laser TVs
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The T3 timer (8-bit) of CC2530 requires understanding of T3CTL, T3CCTL0, T3CC0, T3CCTL1, and T3CC registers. Timer 3/4 is an 8-bit timer with timer/counter/PWM functions. Timer 2, also known as MAC t...[Details]
The frequency calculation formula of the PWM wave generated by the output comparison mode of the timer is: 72M/((2*(arr+1))*(psc+1) ) For example, if you set: PWM_Init(1000-1,72-1); (PWM_Init(arr,psc...[Details]
Embedded System
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