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WEDPN4M72V-100B2M

Description
4M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA219
Categorystorage    storage   
File Size331KB，15 Pages
ManufacturerWhite Electronic Designs Corporation
Websitehttp://www.wedc.com/
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4M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA219

WEDPN4M72V-100B2M Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerWhite Electronic Designs Corporation
package instructionBGA,
Reach Compliance Codeunknow
access modeFOUR BANK PAGE BURST
Maximum access time7 ns
Other featuresAUTO/SELF REFRESH
JESD-30 codeS-PBGA-B219
memory density301989888 bi
Memory IC TypeSYNCHRONOUS DRAM
memory width72
Number of functions1
Number of ports1
Number of terminals219
word count4194304 words
character code4000000
Operating modeSYNCHRONOUS
Maximum operating temperature125 °C
Minimum operating temperature-55 °C
organize4MX72
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Package shapeSQUARE
Package formGRID ARRAY
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Certification statusNot Qualified
Maximum seat height2.64 mm
self refreshYES
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelMILITARY
Terminal formBALL
Terminal pitch1.27 mm
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED

WEDPN4M72V-100B2M Preview

White Electronic Designs
4Mx72 Synchronous DRAM
FEATURES
High Frequency = 100, 125, 133MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 21 x 21mm
Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
4096 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 4M x 72
Weight: WEDPN4M72V-XB2X - 2 grams typical
WEDPN4M72V-XB2X
GENERAL DESCRIPTION
The 32MByte (256Mb) SDRAM is a high-speed CMOS,
dynamic random-access ,memory using 5 chips containing
67,108,864 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 16,777,216-bit banks is organized as 4,096 rows
by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
11 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 256Mb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
BENEFITS
60% SPACE SAVINGS
Reduced part count
Reduced I/O count
• 19% I/O Reduction
Lower inductance and capacitance for low noise
performance
Suitable for hi-reliability applications
Upgradeable to 8M x 72 density with same footprint
WEDPN8M72V-XB2X
* This product is subject to change without notice..
Discrete Approach
11.9
11.9
11.9
11.9
11.9
ACTUAL SIZE
22.3
54
TSOP
54
TSOP
54
TSOP
54
TSOP
54
TSOP
21
White Electronic Designs
WEDPN4M72V-XB2X
21
S
A
V
I
N
G
S
67%
19%
Area
I/O
Count
January 2005
Rev. 2
5 x 265mm
2
= 1328mm
2
5 x 54 pins = 270 pins
1
441mm
2
219 Balls
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FIGURE 1 – PIN CONFIGURATION
WEDPN4M72V-XB2X
TOP VIEW
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
DQ
1
2
DQ
0
3
DQ
14
4
DQ
15
5
V
SS
6
V
SS
7
A
9
8
A
10
9 10
A
11
A
8
11 12
V
CC
V
CC
13 14
DQ
16
DQ
17
15 16
DQ
31
V
SS
DQ
2
DQ
12
DQ
13
V
SS
V
SS
A
0
A
7
A
6
A
1
V
CC
V
CC
DQ
18
DQ
19
DQ
29
DQ
30
DQ
3
DQ
4
DQ
10
DQ
11
V
CC
V
CC
A
2
A
5
A
4
A
3
V
SS
V
SS
DQ
20
DQ
21
DQ
27
DQ
28
DQ
6
DQ
5
DQ
8
DQ
9
V
CC
V
CC
DNU*
DNU
DNU
DNU
V
SS
V
SS
DQ
22
DQ
23
DQ
26
DQ
25
DQ
7
DQML0
V
CC
DQMH0
NC
NC
NC
BA
0
BA
1
NC
NC
NC
DQML1
V
SS
NC
DQ
24
CAS
0
#
WE
0
#
V
CC
CLK
0
NC
RAS
1
#
WE
1
#
V
SS
DQMH1
CLK
1
CS
0
#
RAS
0
#
V
CC
CKE
0
NC
CAS
1
#
CS
1
#
V
SS
NC
CKE
1
V
SS
V
SS
V
CC
V
CC
V
SS
V
CC
V
SS
Vss
V
CC
V
CC
V
SS
V
SS
V
CC
V
CC
V
SS
V
CC
V
SS
V
SS
V
CC
V
CC
NC
CKE
3
V
CC
CS
3
#
NC
NC
CKE
2
V
SS
RAS
2
#
CS
2
#
NC
CLK
3
V
CC
CAS
3
#
RAS
3
#
NC
CLK
2
V
SS
WE
2
#
CAS
2
#
DQ
56
DQMH3
V
CC
WE
3#
DQML3
CKE
4
DQMH4
CLK
4
CAS
4
#
WE
4
#
RAS
4
#
CS
4
#
DQMH2
V
SS
DQML2
DQ
39
DQ
57
DQ
58
DQ
55
DQ
54
NC
NC
DQ
73
DQ
72
DQ
71
DQ
70
DQML4
NC
DQ
41
DQ
40
DQ
37
DQ
38
DQ
60
DQ
59
DQ
53
DQ
52
V
SS
V
SS
DQ
75
DQ
74
DQ
69
DQ
68
V
CC
V
CC
DQ
43
DQ
42
DQ
36
DQ
35
DQ
62
DQ
61
DQ
51
DQ
50
V
CC
V
CC
DQ
77
DQ
76
DQ
67
DQ
66
V
SS
V
SS
DQ
45
DQ
44
DQ
34
DQ
33
Vss
DQ
63
DQ
49
DQ
48
V
CC
V
CC
DQ
79
DQ
78
DQ
65
DQ
64
V
SS
V
SS
DQ
47
DQ
46
DQ
32
V
CC
NOTE: DNU = Do Not Use, to be left unconnected for future upgrades.
* Pin D7 is DNU for 4M x 72, 8M x 72 product, Pin D7 is A12 for 16M x 72 and higher densities.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
WEDPN4M72V-XB2X
FIGURE 2 – FUNCTIONAL BLOCK DIAGRAM
WE0#
RAS 0#
CAS 0#
WE# RAS# CAS#
A0-11
BA0-1
CK0
CKE0
CS0#
DQML0
DQMH0
A0-11
BA0-1
CK
CKE
CS#
DQML
DQMH
DQ0
DQ0
U0
•
•
•
•
•
•
DQ15
•
•
•
•
•
•
DQ15
WE1#
RAS 1#
CAS 1#
WE# RAS# CAS#
A0-11
BA0-1
DQ0
DQ16
CK
1
CKE
1
CS
1
#
DQML
1
DQMH
1
CK
CKE
CS#
DQML
DQMH
U1
•
•
•
•
•
•
DQ15
•
•
•
•
•
•
DQ31
WE2#
RAS 2#
CAS 2#
WE# RAS# CAS#
A0-11
BA0-1
DQ0
DQ32
CK
2
CKE
2
CS
2
#
DQML
2
DQMH
2
CK
CKE
CS#
DQML
DQMH
U2
•
•
•
•
•
•
DQ15
•
•
•
•
•
•
DQ47
WE3#
RAS 3#
CAS 3#
WE# RAS# CAS#
A0-11
BA0-1
DQ0
DQ48
CK
3
CKE
3
CS
3
#
DQML
3
DQMH
3
CK
CKE
CS#
DQML
DQMH
U3
•
•
•
•
•
•
DQ15
•
•
•
•
•
•
DQ63
WE4#
RAS 4#
CAS 4#
WE# RAS# CAS#
A0-11
BA0-1
DQ0
DQ64
CK
4
CKE
4
CS
4
#
DQML
4
DQMH
4
CK
CKE
CS#
DQML
DQMH
U4
•
•
•
•
•
•
DQ15
•
•
•
•
•
•
DQ79
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
The 256Mb SDRAM is designed to operate in 3.3V, low-
power memory systems. An auto refresh mode is provided,
along with a power-saving, power-down mode.
All inputs and outputs are LV
TTL
compatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in order
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access.
WEDPN4M72V-XB2X
performed. After the AUTO REFRESH cycles are complete,
the SDRAM is ready for Mode Register programming.
Because the Mode Register will power up in an unknown
state, it should be loaded prior to applying any operational
command.
REGISTER DEFINITION
MODE REGISTER
The Mode Register is used to define the specific mode
of operation of the SDRAM. This definition includes the
selection of a burst length, a burst type, a CAS latency,
an operating mode and a write burst mode, as shown in
Figure 2. The Mode Register is programmed via the LOAD
MODE REGISTER command and will retain the stored
information until it is programmed again or the device
loses power.
Mode register bits M0-M2 specify the burst length, M3
specifies the type of burst (sequential or interleaved),
M4-M6 specify the CAS latency, M7 and M8 specify the
operating mode, M9 specifies the WRITE burst mode, and
M10 and M11 are reserved for future use.
The Mode Register must be loaded when all banks are
idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these
requirements will result in unspecified operation.
FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0 and BA1 select the bank,
A0-11 select the row). The address bits (A0-7) registered
coincident with the READ or WRITE command are used to
select the starting column location for the burst access.
Prior to normal operation, the SDRAM must be initialized.
The following sections provide detailed information
covering device initialization, register definition, command
descriptions and device operation.
INITIALIZATION
SDRAMs must be powered up and initialized in a predefined
manner. Operational procedures other than those specified
may result in undefined operation. Once power is applied
to V
CC
and V
CCQ
(simultaneously) and the clock is stable
(stable clock is defined as a signal cycling within timing
constraints specified for the clock pin), the SDRAM
requires a 100µs delay prior to issuing any command
other than a COMMAND INHIBIT or a NOP. Starting at
some point during this 100µs period and continuing at
least through the end of this period, COMMAND INHIBIT
or NOP commands should be applied.
Once the 100µs delay has been satisfied with at least
one COMMAND INHIBIT or NOP command having been
applied, a PRECHARGE command should be applied. All
banks must be precharged, thereby placing the device in
the all banks idle state.
Once in the idle state, two AUTO REFRESH cycles must be
January 2005
Rev. 2
4
BURST LENGTH
Read and write accesses to the SDRAM are burst oriented,
with the burst length being programmable, as shown
in Figure 2. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 1, 2, 4
or 8 locations are available for both the sequential and the
interleaved burst types, and a full-page burst is available
for the sequential type. The full-page burst is used in
conjunction with the BURST TERMINATE command to
generate arbitrary burst lengths.
Reserved states should not be used, as unknown operation
or incompatibility with future versions may result.
When a READ or WRITE command is issued, a block of
columns equal to the burst length is effectively selected.
All accesses for that burst take place within this block,
meaning that the burst will wrap within the block if a
boundary is reached. The block is uniquely selected by
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
White Electronic Designs
FIGURE 3 – MODE REGISTER DEFINITION
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
Address Bus
WEDPN4M72V-XB2X
TABLE 1 – BURST DEFINITION
Burst
Length
2
Starting Column
Address
A0
0
1
A0
0
1
0
1
A0
0
1
0
1
0
1
0
1
Order of Accesses Within a Burst
Type = Sequential Type = Interleaved
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
Cn, Cn + 1, Cn + 2
Cn + 3, Cn + 4...
…Cn - 1,
Cn…
0-1
1-0
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
0-1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
Not Supported
Mode Register (Mx)
Reserved* WB Op Mode
CAS Latency
BT
Burst Length
*Should program
M11, M10 = 0, 0
to ensure compatibility
with future devices.
M2 M1M0
0
0
0
0
1
1
1
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
1
2
4
8
Burst Length
M3 = 0
M3 = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
4
Reserved
Reserved
Reserved
Full Page
M3
0
1
Burst Type
Sequential
Interleaved
8
M6 M5 M4
0
0
0
0
1
1
1
1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
CAS Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
A2
0
0
0
0
1
1
1
1
A1
0
0
1
1
A1
0
0
1
1
0
0
1
1
Full
Page
(y)
n = A
0-9/8/7
(location 0-y)
M8
0
-
M7
0
-
M6-M0
Defined
-
Operating Mode
Standard Operation
All other states reserved
M9
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
NOTES:
1. For full-page accesses: y = 256.
2. For a burst length of two, A1-7 select the block-of-two burst; A0 selects the starting
column within the block.
3. For a burst length of four, A2-7 select the block-of-four burst; A0-1 select the starting
column within the block.
4. For a burst length of eight, A3-7 select the block-of-eight burst; A0-2 select the
starting column within the block.
5. For a full-page burst, the full row is selected and A0-7 select the starting column.
6. Whenever a boundary of the block is reached within a given sequence above, the
following access wraps within the block.
7. For a burst length of one, A0-7 select the unique column to be accessed, and Mode
Register bit M3 is ignored.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January 2005
Rev. 2
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
More (Only the first 5 pages are displayed. Please Download Datasheet to view the full content.) >

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Description 4M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA219 4M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA219 4M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA219 4M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA219 4M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA219 4M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA219 4M X 72 SYNCHRONOUS DRAM, 7 ns, PBGA219 4M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA219 4M X 72 SYNCHRONOUS DRAM, 6 ns, PBGA219
memory width 72 72 72 72 72 72 72 72 72
Number of functions 1 1 1 1 1 1 1 1 1
Number of ports 1 1 1 1 1 1 1 1 1
Number of terminals 219 219 219 219 219 219 219 219 219
Maximum operating temperature 125 °C 125 °C 125 °C 125 Cel 85 °C 70 °C 85 °C 70 °C 85 °C
Minimum operating temperature -55 °C -55 °C -55 °C -55 Cel -40 °C - -40 °C - -40 °C
organize 4MX72 4MX72 4MX72 4M X 72 4MX72 4MX72 4MX72 4MX72 4MX72
surface mount YES YES YES Yes YES YES YES YES YES
Temperature level MILITARY MILITARY MILITARY MILITARY INDUSTRIAL COMMERCIAL INDUSTRIAL COMMERCIAL INDUSTRIAL
Terminal form BALL BALL BALL BALL BALL BALL BALL BALL BALL
Terminal location BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM BOTTOM
Is it Rohs certified? incompatible incompatible incompatible - incompatible incompatible incompatible incompatible incompatible
Maker White Electronic Designs Corporation White Electronic Designs Corporation White Electronic Designs Corporation - White Electronic Designs Corporation White Electronic Designs Corporation White Electronic Designs Corporation White Electronic Designs Corporation White Electronic Designs Corporation
package instruction BGA, BGA, BGA, - BGA, BGA, BGA, BGA, BGA,
Reach Compliance Code unknow unknow unknow - unknow unknow unknow unknow unknow
access mode FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST - FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
Maximum access time 7 ns 6 ns 5.5 ns - 6 ns 6 ns 7 ns 7 ns 5.5 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH - AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
JESD-30 code S-PBGA-B219 S-PBGA-B219 S-PBGA-B219 - S-PBGA-B219 S-PBGA-B219 S-PBGA-B219 S-PBGA-B219 S-PBGA-B219
memory density 301989888 bi 301989888 bi 301989888 bi - 301989888 bi 301989888 bi 301989888 bi 301989888 bi 301989888 bi
Memory IC Type SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM - SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM SYNCHRONOUS DRAM
word count 4194304 words 4194304 words 4194304 words - 4194304 words 4194304 words 4194304 words 4194304 words 4194304 words
character code 4000000 4000000 4000000 - 4000000 4000000 4000000 4000000 4000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS - SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code BGA BGA BGA - BGA BGA BGA BGA BGA
Package shape SQUARE SQUARE SQUARE - SQUARE SQUARE SQUARE SQUARE SQUARE
Package form GRID ARRAY GRID ARRAY GRID ARRAY - GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY GRID ARRAY
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Certification status Not Qualified Not Qualified Not Qualified - Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Maximum seat height 2.64 mm 2.64 mm - - 2.64 mm 2.64 mm 2.64 mm 2.64 mm -
self refresh YES YES YES - YES YES YES YES YES
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V - 3.6 V 3.6 V 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V - 3 V 3 V 3 V 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V - 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
technology CMOS CMOS CMOS - CMOS CMOS CMOS CMOS CMOS
Terminal pitch 1.27 mm 1.27 mm 1.27 mm - 1.27 mm 1.27 mm 1.27 mm 1.27 mm 1.27 mm
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED - NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED

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[EEWORLD 25th] Community star figures for April 2011 are announced!
It’s time to announce the community celebrities again! Thank you for your hard work in April, and here are some friends who have made outstanding contributions!April Outstanding Moderator SelectionMod...
EEWORLD社区 Suggestions & Announcements
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What is the relationship between the machine cycle and clock cycle of RH850?
The main frequency of RH850 is set to 120M. What is the conversion relationship between the machine cycle and the clock cycle? Where can I find it? Thank you!...
火火山 Renesas Electronics MCUs
Shortcut:   L0 L1 L2 L3 L4 L5 L6 L7 L8 L9 LA LB LC LD LE LF LG LH LI LJ LK LL LM LN LO LP LQ LR LS LT LU LV LW LX LY LZ M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 MA MB MC MD ME MF MG MH MI MJ MK ML MM MN MO MP MQ MR MS MT MU MV MW MX MY MZ N0 N1 N2 N3 N4 N5 N6 N7 N8 NA NB NC ND NE NF NG NH NI NJ NK NL NM NN NO NP NQ NR NS NT NU NV NX NZ O0 O1 O2 O3 OA OB OC OD OE OF OG OH OI OJ OK OL OM ON OP OQ OR OS OT OV OX OY OZ P0 P1 P2 P3 P4 P5 P6 P7 P8 P9 PA PB PC PD PE PF PG PH PI PJ PK PL PM PN PO PP PQ PR PS PT PU PV PW PX PY PZ Q1 Q2 Q3 Q4 Q5 Q6 Q8 Q9 QA QB QC QE QF QG QH QK QL QM QP QR QS QT QV QW QX QY R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 RA RB RC RD RE RF RG RH RI RJ RK RL RM RN RO RP RQ RR RS RT RU RV RW RX RY RZ

Popular Components

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  5. H845K3AAA
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Popular Articles

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  4. Industrial AI company Jushi Technology completes A+ round of financing of hundreds of millions of yuan to strengthen competition in the semiconductor field
  5. STM8 routine collection (register version)
  6. BYD is engaged in "acupuncture", Lantu is developing "amber" and "mica", they all have a bright future
  7. e-Network launches road test of essential instruments for Keysight's smart test bench
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Technical ResourceMore

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  6. MAX7365,pdf( I2C-interfaced peripheral that provides microprocessors)
  7. Design and Synthesis of I2C Controller Based on Verilog
  8. Temperature characteristics of LDMOS power amplifier and design of temperature compensation circuit
  9. PL2303 Driver
  10. Several issues on the design of intermittent flyback transformer

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