MP1230A/31A/32A
CMOS Microprocessor Compatible
Double-Buffered 12-Bit
Digital-to-Analog Converter
FEATURES
•
Superior Ruggedized 1230 Series: 2 KV ESD
•
Four Quadrant Multiplication
•
Stable, More Accurate Segmented DAC Approach
– 0.2 ppm/°C Linearity Tempco
– 2 ppm/°C Max Gain Error Tempco
– Lowest Sensitivity to Amplifier Offset
– Lowest Output Capacitance (C
OUT
= 80pF)
– Lower Glitch Energy
•
Monotonic over Temperature Range
•
•
•
•
•
Lower Data Bus Feedthrough @ CS = 1
V
DD
from +11 V to +16 V
Latch-Up Free CMOS Technology
12-Bit Bus Version: MP1208/1209/1210
16-Bit Upgrade: MP7636A
GENERAL DESCRIPTION
The MP1230A series are superior pin for pin replacements
for the 1230 series. The MP1230A series is manufactured using
advanced thin film resistors on a double metal CMOS process
which promotes significant improvements in reliability, latch-up
free performance and ESD protection.
The MP1230A series incorporates a unique decoding tech-
nique yielding lower glitch, higher speed and excellent accuracy
over temperature and time. 12-bit linearity is achieved without
trimming. Outstanding features include:
–
Stability: integral and differential linearity tempcos are rated
at 0.2 ppm/
°
C typical. Monotonicity is guaranteed over all
temperature ranges. Scale factor tempco is a low 2 ppm/
°
C
maximum.
–
Low Output Capacitance: Due to smaller MOSFET switch
geometries allowed by decoding, the output capacitance at
I
OUT1
and I
OUT2
is a low 80pF / 40pF and 25pF / 65 pF. This
less than half the competitive DAC 1230 series. Lower ca-
pacitance allows the MP1230A series to achieve settling
times faster than 1
µ
s for a 10 V step.
Low Sensitivity to Output Amplifier Offset: The linearity er-
ror caused by amplifier offset is reduced by a factor of 2 in the
MP1230A series over conventional R-2R DACs.
–
The MP1230A series uses a circuit which reduces transients
in the supplies caused by DATA bus transitions at CS = 1.
SIMPLIFIED BLOCK DIAGRAM
V
DD
INPUT LATCH
DB11-DB4
DB3-DB0
BYTE1/BYTE2
D
8
8
V
REF
R
FB
V
REF
I
OUT1
I
OUT2
DAC LATCH
D
Q
Q
8
12
LE
LE
D
4
Q
4
12
CS
WR1
LE
XFER WR2 DGND
AGND
Rev. 2.00
1
MP1230A/31A/32A
ORDERING INFORMATION
Package
Type
Plastic Dip
Plastic Dip
Plastic Dip
SOIC
SOIC
SOIC
Temperature
Range
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
–40 to +85
°
C
Part No.
MP1230ABN
MP1231ABN
MP1232ABN
MP1230ABS
MP1231ABS
MP1232ABS
INL
(LSB)
+1/2
+1
+2
+1/2
+1
+2
DNL
(LSB)
+3/4
+1
+2
+3/4
+1
+2
Gain Error
(% FSR)
+0.4
+0.4
+0.4
+0.4
+0.4
+0.4
PIN CONFIGURATIONS
CS
WR1
AGND
DB7
DB6
DB5
DB4
V
REF
R
FB
DGND
1
2
3
4
5
6
7
8
9
10
See Packaging Section for Package Dimensions
20
19
18
17
16
15
14
13
12
11
V
DD
BYTE1/BYTE2
WR2
XFER
DB8 (DB0, LSB)
DB9 (DB1)
DB10 (DB2)
DB11 MSB (DB3)
I
OUT2
I
OUT1
CS
WR1
AGND
DB7
DB6
DB5
DB4
V
REF
R
FB
DGND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
DD
BYTE1/BYTE2
WR2
XFER
DB8 (DB0, LSB)
DB9 (DB1)
DB10 (DB2)
DB11 MSB (DB3)
I
OUT2
I
OUT1
20 Pin PDIP (0.300”)
N20
20 Pin SOIC (Jedec, 0.300”)
S20
PIN OUT DEFINITIONS
PIN NO.
1
2
3
4
5
6
7
8
9
10
11
NAME
CS
WR1
AGND
DB7
DB6
DB5
DB4
V
REF
R
FB
DGND
I
OUT1
DESCRIPTION
Chip Select (Active Low)
Write 1 (Active Low)
Analog Ground
Data Input Bit 7
Data Input Bit 6
Data Input Bit 5
Data Input Bit 4
Reference Input Voltage
Feedback Resistor
Digital Ground
Current Output 1
20
16
17
18
19
DB8 (DB0)
XFER
WR2
BYTE1/
BYTE2
V
DD
14
15
DB10 (DB2)
DB9 (DB1)
PIN NO.
12
13
NAME
I
OUT2
DB11 (DB3)
DESCRIPTION
Current Output 2
Data Input Bit 11 (MSB)
Data Input Bit 3
Data Input Bit 10
Data Input Bit 2
Data Input Bit 9
Data Input Bit 1
Data Input Bit 8
Data Input Bit 0 (LSB)
Transfer Control Signal (Active Low)
Write 2 (Active Low)
Byte Sequence Control
Positive Power Supply
Rev. 2.00
2
MP1230A/31A/32A
ELECTRICAL CHARACTERISTICS
(V
DD
= + 15 V, V
REF
= +10 V unless otherwise noted)
Parameter
STATIC PERFORMANCE
1
Resolution (All Grades)
Integral Non-Linearity
(Relative Accuracy)
MP1230ABN/ATD/ABS
MP1231ABN/ATD/ABS
MP1232ABN/ATD/ABS
Differential Non-Linearity
MP1230ABN/ATD/ABS
MP1231ABN/ATD/ABS
MP1232ABN/ATD/ABS
Gain Error
Gain Temperature Coefficient
2
Power Supply Rejection Ratio
Output Leakage Current
DYNAMIC PERFORMANCE
2
Current Settling Time
AC Feedthrough at I
OUT1
REFERENCE INPUT
Input Resistance
DIGITAL INPUTS
Logical “1” Voltage
Logical “0” Voltage
Input Leakage Current
Input Capacitance
2
ANALOG OUTPUTS
2
Output Capacitance
C
OUT1
C
OUT1
C
OUT2
C
OUT2
POWER SUPPLY
Functional Voltage Range
4
Supply Current
V
DD
I
DD
+4.5
1.2
+16
2.0
+4.5
+16
2.0
V
mA
80
40
65
25
100
60
85
45
100
60
85
45
pF
pF
pF
pF
DAC Inputs all 1’s
DAC Inputs all 0’s
DAC Inputs all 1’s
DAC Inputs all 0’s
V
IH
V
IL
I
LKG
10
3.0
2.4
0.8
+1
3.0
0.8
+1
V
V
µA
pF
R
IN
5
10
20
5
20
kΩ
t
S
F
T
1.0
1.0
µsec
mV p-p
N
INL
+1/2
+1
+2
DNL
+3/4
+1
+2
GE
TC
GE
PSRR
I
OUT
0.5
5
1
+20
+10
+0.4
+3/4
+1
+2
+0.4
+2
+20
+200
% FSR
ppm/°C
ppm/%
nA
R
L
=100Ω, C
L
=13pF
Full Scale Change to 1/2 LSB
V
REF
=100kHz, 20Vp-p, sinewave
Using Internal R
FB
∆Gain/∆Temperature
|∆Gain/∆V
DD
| ∆V
DD
= + 0.25V
+1/2
+1
+2
LSB
12
12
Bits
LSB
Best Fit Straight Line Spec.
(Max INL – Min INL) / 2
Symbol
Min
25
°
C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
FSR = Full Scale Range
V
IN
= 0, 5 V
All digital inputs = 0 V or all = 5 V
Rev. 2.00
3
MP1230A/31A/32A
ELECTRICAL CHARACTERISTICS (CONT’D)
Parameter
SWITCHING
CHARACTERISTICS
2, 3
Chip Select to Write Set-Up Time
Chip Select to Write Hold Time
Data Valid to Write Set-Up Time
Data Valid to Write Hold Time
Write Pulse Width,
t
CS
t
CH
t
DS
t
DH
t
WR
200
10
100
90
100
100
0
50
70
50
ns
ns
ns
ns
ns
Symbol
Min
25
°
C
Typ
Max
Tmin to Tmax
Min
Max
Units
Test Conditions/Comments
NOTES:
1
2
3
4
Full Scale Range (FSR) is 10V.
Guaranteed but not production tested.
See timing diagram.
Specified values guarantee functionality. Refer to other parameters for accuracy.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (T
A
= +25
°
C unless otherwise noted)
1, 2
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V
Digital Input Voltage to GND . . . . GND –0.5 to V
DD
+0.5 V
I
OUT1
, I
OUT2
to GND . . . . . . . . . . . . . . . . GND –0.5 to +6.5 V
V
REF
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
V
RFB
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V
(Functionality Guaranteed +0.5 V)
Storage Temperature . . . . . . . . . . . . . . . . . –65
°
C to +150
°
C
Lead Temperature (Soldering, 10 seconds) . . . . . . +300
°
C
Package Power Dissipation Rating to 75
°
C
CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 900mW
Derates above 75
°
C . . . . . . . . . . . . . . . . . . . . . 12mW/
°
C
NOTES:
1
Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
2
Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps
(HP5082-2835) from input pin to the supplies.
All inputs have protection diodes
which will protect the device from short
transients outside the supplies of less than 100mA for less than 100
µ
s.
3
GND refers to AGND and DGND.
Rev. 2.00
4
MP1230A/31A/32A
TIMING DIAGRAM
V
IH
V
IL
t
WR
50%
t
DS
50%
50%
t
CS
50%
t
CH
50%
CS, BYTE1/BYTE2
V
IH
WR
V
IL
V
IH
DATA BITS
V
IL
t
DH
50%
t
S
SETTLED TO
+0.01%
I
OUT1
, I
OUT2
DEFINITION OF CONTROL SIGNALS:
CS:
WR1:
Chip Select.(Active low)
It will enable WR1.
Write 1 (Active low)
The WR1 is used to load the digital data bits (DB) into
the input latch.
I
OUT2
:
R
FB
:
DAC Current Output 2 Bus.
I
OUT2
is a complement of I
OUT1
.
Feedback Resistor.
This internal feedback resistor should always be used
(not an external resistor) since it matches the resistors
in the DAC and tracks these resistors over tempera-
ture.
Reference Voltage Input.
This input connects an external precision voltage
source to the internal DAC. The V
REF
can be selected
over the range of +25V to –25V or the analog signal for
a 4-quadrant multiplying mode application.
Power Supply Voltage.
This is the power supply pin for the part. The V
DD
can
be from +5 V DC to +15 V DC, however optimum volt-
age is +12 to +15 V DC.
BYTE1/BYTE2: Byte sequence control.
The BYTE1/BYTE2 control pin is used to select both
MSB and LSB input latches.
WR2:
XFER:
Write 2 (Active low)
It will enable XFER.
Transfer control signal (Active low)
This signal in combination with WR2 causes the 16-bit
data which is available in the input latches to transfer
to the DAC register
V
REF
:
V
DD
:
DB0 to DB11: Digital Inputs.
DB0 is the least significant digital input (LSB) and
DB11 is the most significant digital input (MSB).
I
OUT1
:
DAC Current Output 1 Bus.
I
OUT1
is a maximum for a digital code of all 1’s in the
DAC register, and is zero for all 0’s in the DAC register.
AGND: Analog Ground
Back gate of the DAC N-channel current steering
switches.
DGND: Digital Ground
Rev. 2.00
5
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