MP1230A datasheet, PDF - EEWORLD Datasheet

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MP1230A: DescriptionCMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter; File Size83KB，12 Pages; ManufacturerExar [Exar Corporation]

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MP1230A Overview

CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter

MP1230A Preview

MP1230A/31A/32A

CMOS Microprocessor Compatible

Double-Buffered 12-Bit

Digital-to-Analog Converter

FEATURES

•

Superior Ruggedized 1230 Series: 2 KV ESD

•

Four Quadrant Multiplication

•

Stable, More Accurate Segmented DAC Approach

– 0.2 ppm/°C Linearity Tempco

– 2 ppm/°C Max Gain Error Tempco

– Lowest Sensitivity to Amplifier Offset

– Lowest Output Capacitance (C

OUT

= 80pF)

– Lower Glitch Energy

•

Monotonic over Temperature Range

•

Lower Data Bus Feedthrough @ CS = 1

from +11 V to +16 V

Latch-Up Free CMOS Technology

12-Bit Bus Version: MP1208/1209/1210

16-Bit Upgrade: MP7636A

GENERAL DESCRIPTION

The MP1230A series are superior pin for pin replacements

for the 1230 series. The MP1230A series is manufactured using

advanced thin film resistors on a double metal CMOS process

which promotes significant improvements in reliability, latch-up

free performance and ESD protection.

The MP1230A series incorporates a unique decoding tech-

nique yielding lower glitch, higher speed and excellent accuracy

over temperature and time. 12-bit linearity is achieved without

trimming. Outstanding features include:

–

Stability: integral and differential linearity tempcos are rated

at 0.2 ppm/

C typical. Monotonicity is guaranteed over all

temperature ranges. Scale factor tempco is a low 2 ppm/

maximum.

–

Low Output Capacitance: Due to smaller MOSFET switch

geometries allowed by decoding, the output capacitance at

OUT1

and I

OUT2

is a low 80pF / 40pF and 25pF / 65 pF. This

less than half the competitive DAC 1230 series. Lower ca-

pacitance allows the MP1230A series to achieve settling

times faster than 1

s for a 10 V step.

Low Sensitivity to Output Amplifier Offset: The linearity er-

ror caused by amplifier offset is reduced by a factor of 2 in the

MP1230A series over conventional R-2R DACs.

–

The MP1230A series uses a circuit which reduces transients

in the supplies caused by DATA bus transitions at CS = 1.

SIMPLIFIED BLOCK DIAGRAM

INPUT LATCH

DB11-DB4

DB3-DB0

BYTE1/BYTE2

REF

OUT1

OUT2

DAC LATCH

WR1

XFER WR2 DGND

AGND

Rev. 2.00

MP1230A/31A/32A

ORDERING INFORMATION

Package

Type

Plastic Dip

SOIC

Temperature

Range

–40 to +85

Part No.

MP1230ABN

MP1231ABN

MP1232ABN

MP1230ABS

MP1231ABS

MP1232ABS

INL

(LSB)

+1/2

DNL

(LSB)

+3/4

Gain Error

(% FSR)

+0.4

PIN CONFIGURATIONS

WR1

AGND

DB7

DB6

DB5

DB4

REF

DGND

See Packaging Section for Package Dimensions

BYTE1/BYTE2

WR2

XFER

DB8 (DB0, LSB)

DB9 (DB1)

DB10 (DB2)

DB11 MSB (DB3)

OUT2

OUT1

WR1

AGND

DB7

DB6

DB5

DB4

REF

DGND

BYTE1/BYTE2

WR2

XFER

DB8 (DB0, LSB)

DB9 (DB1)

DB10 (DB2)

DB11 MSB (DB3)

OUT2

OUT1

20 Pin PDIP (0.300”)

N20

20 Pin SOIC (Jedec, 0.300”)

S20

PIN OUT DEFINITIONS

PIN NO.

NAME

WR1

AGND

DB7

DB6

DB5

DB4

REF

DGND

OUT1

DESCRIPTION

Chip Select (Active Low)

Write 1 (Active Low)

Analog Ground

Data Input Bit 7

Data Input Bit 6

Data Input Bit 5

Data Input Bit 4

Reference Input Voltage

Feedback Resistor

Digital Ground

Current Output 1

DB8 (DB0)

XFER

WR2

BYTE1/

BYTE2

DB10 (DB2)

DB9 (DB1)

PIN NO.

NAME

OUT2

DB11 (DB3)

DESCRIPTION

Current Output 2

Data Input Bit 11 (MSB)

Data Input Bit 3

Data Input Bit 10

Data Input Bit 2

Data Input Bit 9

Data Input Bit 1

Data Input Bit 8

Data Input Bit 0 (LSB)

Transfer Control Signal (Active Low)

Write 2 (Active Low)

Byte Sequence Control

Positive Power Supply

Rev. 2.00

MP1230A/31A/32A

ELECTRICAL CHARACTERISTICS

= + 15 V, V

REF

= +10 V unless otherwise noted)

Parameter

STATIC PERFORMANCE

Resolution (All Grades)

Integral Non-Linearity

(Relative Accuracy)

MP1230ABN/ATD/ABS

MP1231ABN/ATD/ABS

MP1232ABN/ATD/ABS

Differential Non-Linearity

MP1230ABN/ATD/ABS

MP1231ABN/ATD/ABS

MP1232ABN/ATD/ABS

Gain Error

Gain Temperature Coefficient

Power Supply Rejection Ratio

Output Leakage Current

DYNAMIC PERFORMANCE

Current Settling Time

AC Feedthrough at I

OUT1

REFERENCE INPUT

Input Resistance

DIGITAL INPUTS

Logical “1” Voltage

Logical “0” Voltage

Input Leakage Current

Input Capacitance

ANALOG OUTPUTS

Output Capacitance

OUT1

OUT2

POWER SUPPLY

Functional Voltage Range

Supply Current

+4.5

1.2

+16

2.0

+4.5

+16

2.0

100

DAC Inputs all 1’s

DAC Inputs all 0’s

DAC Inputs all 1’s

DAC Inputs all 0’s

LKG

3.0

2.4

0.8

3.0

0.8

µA

kΩ

1.0

µsec

mV p-p

INL

+1/2

DNL

+3/4

PSRR

OUT

0.5

+20

+10

+0.4

+3/4

+0.4

+20

+200

% FSR

ppm/°C

ppm/%

=100Ω, C

=13pF

Full Scale Change to 1/2 LSB

REF

=100kHz, 20Vp-p, sinewave

Using Internal R

∆Gain/∆Temperature

|∆Gain/∆V

| ∆V

= + 0.25V

+1/2

LSB

Bits

LSB

Best Fit Straight Line Spec.

(Max INL – Min INL) / 2

Symbol

Min

Typ

Max

Tmin to Tmax

Min

Max

Units

Test Conditions/Comments

FSR = Full Scale Range

= 0, 5 V

All digital inputs = 0 V or all = 5 V

Rev. 2.00

MP1230A/31A/32A

ELECTRICAL CHARACTERISTICS (CONT’D)

Parameter

SWITCHING

CHARACTERISTICS

2, 3

Chip Select to Write Set-Up Time

Chip Select to Write Hold Time

Data Valid to Write Set-Up Time

Data Valid to Write Hold Time

Write Pulse Width,

200

100

Symbol

Min

Typ

Max

Tmin to Tmax

Min

Max

Units

Test Conditions/Comments

NOTES:

Full Scale Range (FSR) is 10V.

Guaranteed but not production tested.

See timing diagram.

Specified values guarantee functionality. Refer to other parameters for accuracy.

Specifications are subject to change without notice

ABSOLUTE MAXIMUM RATINGS (T

= +25

C unless otherwise noted)

1, 2

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V

Digital Input Voltage to GND . . . . GND –0.5 to V

+0.5 V

OUT1

, I

OUT2

to GND . . . . . . . . . . . . . . . . GND –0.5 to +6.5 V

REF

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V

RFB

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V

(Functionality Guaranteed +0.5 V)

Storage Temperature . . . . . . . . . . . . . . . . . –65

C to +150

Lead Temperature (Soldering, 10 seconds) . . . . . . +300

Package Power Dissipation Rating to 75

CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 900mW

Derates above 75

C . . . . . . . . . . . . . . . . . . . . . 12mW/

NOTES:

Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating

conditions for extended periods may affect device reliability.

Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps

(HP5082-2835) from input pin to the supplies.

All inputs have protection diodes

which will protect the device from short

transients outside the supplies of less than 100mA for less than 100

GND refers to AGND and DGND.

Rev. 2.00

MP1230A/31A/32A

TIMING DIAGRAM

50%

CS, BYTE1/BYTE2

DATA BITS

50%

SETTLED TO

+0.01%

OUT1

, I

OUT2

DEFINITION OF CONTROL SIGNALS:

CS:

WR1:

Chip Select.(Active low)

It will enable WR1.

Write 1 (Active low)

The WR1 is used to load the digital data bits (DB) into

the input latch.

OUT2

DAC Current Output 2 Bus.

OUT2

is a complement of I

OUT1

Feedback Resistor.

This internal feedback resistor should always be used

(not an external resistor) since it matches the resistors

in the DAC and tracks these resistors over tempera-

ture.

Reference Voltage Input.

This input connects an external precision voltage

source to the internal DAC. The V

REF

can be selected

over the range of +25V to –25V or the analog signal for

a 4-quadrant multiplying mode application.

Power Supply Voltage.

This is the power supply pin for the part. The V

can

be from +5 V DC to +15 V DC, however optimum volt-

age is +12 to +15 V DC.

BYTE1/BYTE2: Byte sequence control.

The BYTE1/BYTE2 control pin is used to select both

MSB and LSB input latches.

WR2:

XFER:

Write 2 (Active low)

It will enable XFER.

Transfer control signal (Active low)

This signal in combination with WR2 causes the 16-bit

data which is available in the input latches to transfer

to the DAC register

REF

DB0 to DB11: Digital Inputs.

DB0 is the least significant digital input (LSB) and

DB11 is the most significant digital input (MSB).

OUT1

DAC Current Output 1 Bus.

OUT1

is a maximum for a digital code of all 1’s in the

DAC register, and is zero for all 0’s in the DAC register.

AGND: Analog Ground

Back gate of the DAC N-channel current steering

switches.

DGND: Digital Ground

Rev. 2.00

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MP1230A Related Products

	MP1230A	MP1231A	MP1230ABN	MP1232A	MP1232ABS	MP1232ABN	MP1231ABS	MP1231ABN	MP1230ABS
Description	CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter	CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter	CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter	CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter	CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter	CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter	CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter	CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter	CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter

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