ZL50018
2 K Digital Switch with Enhanced
Stratum 3 DPLL
Data Sheet
Features
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2048 channel x 2048 channel non-blocking digital
Time Division Multiplex (TDM) switch at 8.192
and 16.384 Mbps or using a combination of ports
running at 2.048, 4.096, 8.192 and/or
16.384 Mbps
32 serial TDM input, 32 serial TDM output
streams
Integrated Digital Phase-Locked Loop (DPLL)
exceeds Telcordia GR-1244-CORE Stratum 3
specifications
Output clocks have less than 1 ns of jitter (except
for the 1.544 MHz output)
DPLL provides holdover, freerun and jitter
attenuation features with four independent
reference source inputs
Programmable key DPLL parameters (filter
corner frequency, locking range, auto-holdover
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Ordering Information
ZL50018GAC
ZL50018QCG1
ZL50018GAG2
256 Ball PBGA
256 Lead LQFP*
256 Ball PBGA**
Trays
Trays, Bake &
Drypack
Trays, Bake &
Drypack
September 2011
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*Pb Free Matte Tin
**Pb Free Tin/Silver/Copper
-40C to +85C
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hysteresis range, phase slope, lock detector
range)
Exceptional input clock cycle to cycle variation
tolerance (20 ns for all rates)
Output streams can be configured as bi-
directional for connection to backplanes
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V
DD_CORE
V
DD_IO
V
DD_COREA
V
DD_IOA
V
SS
RESET
ODE
STi[31:0]
FPi
CKi
MODE_4M0
MODE_4M1
REF0
REF1
REF2
REF3
REF_FAIL0
REF_FAIL1
REF_FAIL2
REF_FAIL3
S/P Converter
Data Memory
P/S Converter
STio[31:0]
Input Timing
Connection Memory
Output HiZ
Control
STOHZ[15:0]
DPLL
Output Timing
FPo[3:0]
CKo[5:0]
FPo_OFF[2:0]
OSC_EN
OSC
Internal Registers &
Microprocessor Interface
Test Port
TDi
OSCo
DS_RD
R/W_WR
Figure 1 - ZL50018 Functional Block Diagram
Zarlink Semiconductor US Patent No. 5,602,884, UK Patent No. 0772912,
France Brevete S.G.D.G. 0772912; Germany DBP No. 69502724.7-08
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2004-2011, Zarlink Semiconductor Inc. All Rights Reserved.
MOT_INTEL
DTA_RDY
D[15:0]
A[13:0]
OSCi
TRST
TMS
TCK
TDo
IRQ
CS
ZL50018
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Data Sheet
Per-stream input and output data rate conversion selection at 2.048, 4.096, 8.192 or 16.384 Mbps. Input and
output data rates can differ
Per-stream high impedance control outputs (STOHZ) for up to 16 output streams
Per-stream input bit delay with flexible sampling point selection
Per-stream output bit and fractional bit advancement
Per-channel ITU-T G.711 PCM A-Law/-Law Translation
Multiple frame pulse and reference clock output
Input clock: 4.096 MHz, 8.192 MHz, 16.384 MHz
Input frame pulses: 61 ns, 122 ns, 244 ns
Per-channel constant or variable throughput delay for frame integrity and low latency applications
Per Stream Bit Error Rate Test circuits
Per-channel high impedance output control
Per-channel message mode
Control interface compatible with Intel and Motorola 16-bit non-multiplexed buses
Connection memory block programming
Supports ST-BUS and GCI-Bus standards for input and output timing
IEEE-1149.1 (JTAG) test port
3.3 V I/O with 5 V tolerant inputs; 1.8 V core voltage
Applications
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PBX and IP-PBX
Small and medium digital switching platforms
Wireless base stations and controllers
Remote access servers and concentrators
Multi service access platforms
Digital Loop Carriers
Computer Telephony Integration
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Zarlink Semiconductor Inc.
ZL50018
Description
Data Sheet
The ZL50018 is a maximum 2,048 x 2,048 channel non-blocking digital Time Division Multiplex (TDM) switch. It has
thirty-two input streams (STi0 - 31) and thirty-two output streams (STio0 - 31). The device can switch 64 kbps and
Nx64 kbps TDM channels from any input stream to any output stream. Each of the input and output streams can be
independently programmed to operate at any of the following data rates: 2.048, 4.096, 8.192 or 16.384 Mbps. The
ZL50018 provides up to sixteen high impedance control outputs (STOHZ0 - 15) to support the use of external
tristate drivers for the first sixteen output streams (STio0 - 15). The output streams can be configured to operate in
bi-directional mode, in which case STi0 - 31 will be ignored.
The device contains two types of internal memory - data memory and connection memory. There are four modes of
operation - Connection Mode, Message Mode, BER Mode and High Impedance Mode. In Connection Mode, the
contents of the connection memory define, for each output stream and channel, the source stream and channel
(the actual data to be output is stored in the data memory). In Message Mode, the connection memory is used for
the storage of microprocessor data. Using Zarlink's Message Mode capability, microprocessor data can be
broadcast to the data output streams on a per-channel basis. This feature is useful for transferring control and
status information for external circuits or other TDM devices. In BER mode the output channel data is replaced with
a pseudorandom bit sequence (PRBS) from one of 32 PRBS generators that generates a 2
15
-1 pattern. On the
input side channels can be routed to one of 32 bit error detectors. In high impedance mode the selected output
channel can be put into a high impedance state.
When the device is operating as a timing master, the internal digital PLL is in use. In this mode, an external
20.000 MHz crystal is required for the on-chip crystal oscillator. The DPLL is phase-locked to one of four input
reference signals (which can be 8 kHz, 1.544, 2.048, 4.096, 8.192, 16.384 or 19.44 MHz provided on REF0 - 3).
The on-chip DPLL operates in normal, holdover or freerun mode and offers jitter attenuation. The jitter attenuation
function exceeds the Stratum 3 specification.
The configurable non-multiplexed microprocessor port allows users to program various device operating modes
and switching configurations. Users can employ the microprocessor port to perform register read/write, connection
memory read/write, and data memory read operations. The port is configurable to interface with either Motorola or
Intel-type microprocessors.
The device also supports the mandatory requirements of the IEEE-1149.1 (JTAG) standard via the test port.
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Zarlink Semiconductor Inc.
ZL50018
Table of Contents
Data Sheet
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
1.0 Pinout Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.1 BGA Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2 QFP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.0 Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.0 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.0 Data Rates and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1 External High Impedance Control, STOHZ0 - 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Input Clock (CKi) and Input Frame Pulse (FPi) Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.0 ST-BUS and GCI-Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.0 Output Timing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
7.0 Data Input Delay and Data Output Advancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.1 Input Bit Delay Programming. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.2 Input Bit Sampling Point Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
7.3 Output Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.4 Fractional Output Bit Advancement Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.5 External High Impedance Control Advancement. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.0 Data Delay Through the Switching Paths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.1 Variable Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2 Constant Delay Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.0 Connection Memory Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.0 Connection Memory Block Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.1 Memory Block Programming Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
11.0 Device Operation in Master Mode and Slave Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
11.1 Master Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11.2 Divided Slave Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
11.3 Multiplied Slave Mode Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.0 Overall Operation of the DPLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
12.1 DPLL Timing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.1.1 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.1.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.1.3 Automatic Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.1.3.1 Automatic Reference Switching Without Preferences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
12.1.3.2 Automatic Reference Switching With Preference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
12.1.4 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1.5 Software Controlled Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
12.1.6 DPLL Internal Reset Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.0 DPLL Frequency Behaviour . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.1 Input Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
13.2 Input Frequencies Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.3 Output Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
13.4 Pull-In/Hold-In Range (also called Locking Range). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
14.0 Jitter Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.1 Input Clock Cycle to Cycle Timing Variation Tolerance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.2 Input Jitter Acceptance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
14.3 Jitter Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15.0 DPLL Specific Functions and Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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Zarlink Semiconductor Inc.
ZL50018
Table of Contents
Data Sheet
15.1 Lock Detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15.2 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15.3 Phase Alignment Speed (Phase Slope) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
15.4 Fast Locking Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
15.5 Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
15.6 Single Period Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
15.7 Multiple Period Reference Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
16.0 Microprocessor Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
17.0 Device Reset and Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
17.1 Power-up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
17.2 Device Initialization on Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
17.3 Software Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
18.0 Pseudo-random Bit Generation and Error Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
19.0 PCM A-law/m-law Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
20.0 Quadrant Frame Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
21.0 JTAG Port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
21.1 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
21.2 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
21.3 Test Data Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
21.4 BSDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
22.0 Register Address Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
23.0 Detailed Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
24.0 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
24.1 Memory Address Mappings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
24.2 Connection Memory Low (CM_L) Bit Assignment. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
24.3 Connection Memory High (CM_H) Bit Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
25.0 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
25.1 OSCi Master Clock Requirement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
25.1.1 External Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
25.1.2 External Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
26.0 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
27.0 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
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Zarlink Semiconductor Inc.
MCU
京公网安备 11010802033920号
EEWORLD
