Data Sheet
FEATURES
Low power octal DACs
AD5629R:
12 bits
AD5669R:
16 bits
2.6 mm × 2.6 mm 16-ball WLCSP
4 mm × 4 mm 16-lead LFCSP and 16-lead TSSOP
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
Power down to 400 nA at 5 V, 200 nA at 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale or midscale
3 power-down functions
Hardware LDAC and CLR functions
I
2
C-compatible serial interface supports standard (100 kHz)
and fast (400 kHz) modes
E
E
A
A
A
Octal, 12-/16-Bit, I
2
C,
denseDACs
with 5 ppm/°C On-Chip Reference
AD5629R/AD5669R
FUNCTIONAL BLOCK DIAGRAM
9B
V
DD
V
REFIN
/V
REFOUT
1.25V/2.5V REF
BUFFER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
STRING
DAC B
BUFFER
STRING
DAC C
BUFFER
STRING
DAC D
BUFFER
STRING
DAC E
BUFFER
STRING
DAC F
BUFFER
STRING
DAC G
BUFFER
STRING
DAC H
AD5629R/AD5669R
LDAC
SCL
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
INPUT
REGISTER
V
OUT
A
V
OUT
B
SDA
INTERFACE LOGIC
V
OUT
C
V
OUT
D
V
OUT
E
A0
V
OUT
F
APPLICATIONS
8B
V
OUT
G
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
V
OUT
H
POWER-ON RESET
POWER-DOWN LOGIC
08819-001
LDAC CLR
GND
Figure 1.
GENERAL DESCRIPTION
10B
The
AD5629R/AD5669R
devices are low power, octal, 12-/16-
bit, buffered voltage-output DACs. All devices are guaranteed
monotonic by design.
The
AD5629R/AD5669R
have an on-chip reference with an
internal gain of 2. The
AD5629R-1/AD5669R-1
have a 1.25 V,
5 ppm/°C reference, giving a full-scale output range of 2.5 V.
The
AD5629R-2/AD5629R-3
and the
AD5669R-2/AD5669R-3
have a 2.5 V 5 ppm/°C reference, giving a full-scale output range
of 5 V depending on the option selected. Devices with 1.25 V
reference selected operate from a single 2.7 V to 5.5 V supply.
Devices with 2.5 V reference selected operate from 4.5 V to 5.5 V.
The on-chip reference is off at power-up, allowing the use of an
external reference. The internal reference is enabled via a
software write.
The parts incorporate a power-on reset circuit to ensure that
the DAC output powers up to 0 V (AD5629R-1/AD5629R-2,
AD5669R-1/AD5669R-2)
or midscale (AD5629R-3/AD5669R-3)
and remains powered up at this level until a valid write takes place.
The part contains a power-down feature that reduces the current
consumption of the device to 400 nA at 5 V and provides software-
selectable output loads while in power-down mode for any or
all DAC channels.
PRODUCT HIGHLIGHTS
1B
1.
2.
3.
4.
5.
Octal, 12-/16-bit DACs.
On-chip 1.25 V/2.5 V, 5 ppm/°C reference.
Available in 16-lead LFCSP and TSSOP, and 16-ball
WLCSP.
Power-on reset to 0 V or midscale.
Power-down capability. When powered down, the DAC
typically consumes 200 nA at 3 V and 400 nA at 5 V.
Rev. E
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Trademarks and registered trademarks are the property of their respective owners.
AD5629R/AD5669R
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
AC Characteristics........................................................................ 6
I
2
C Timing Characteristics .......................................................... 7
Absolute Maximum Ratings............................................................ 9
ESD Caution .................................................................................. 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 12
Terminology .................................................................................... 19
Theory of Operation ...................................................................... 21
Digital-to-Analog Converter (DAC) Section ......................... 21
Data Sheet
Resistor String ............................................................................. 21
Internal Reference ...................................................................... 21
Output Amplifier........................................................................ 22
Serial Interface ............................................................................ 22
Write Operation.......................................................................... 22
Read Operation........................................................................... 22
Input Shift Register .................................................................... 23
Multiple Byte Operation ............................................................ 23
Internal Reference Register ....................................................... 24
Power-On Reset .......................................................................... 24
Power-Down Modes .................................................................. 25
Clear Code Register ................................................................... 25
LDAC Function .......................................................................... 27
Power Supply Bypassing and Grounding ................................ 27
Outline Dimensions ....................................................................... 28
Ordering Guide .......................................................................... 30
REVISION HISTORY
9/2016—Rev. D to Rev. E
Change to Read Operation Section .............................................. 22
4/2014—Rev. C to Rev. D
Change to V
OUT
B, V
OUT
C, V
OUT
D, V
OUT
E, V
OUT
G, V
OUT
H Ball
Numbers; Table 6 ............................................................................ 11
2/2014—Rev. B to Rev. C
Change to Table 6 ........................................................................... 11
Changes to Figure 38, Figure 39, and Figure 40 ......................... 17
Changes to Ordering Guide .......................................................... 30
2/2013—Rev.
A to Rev. B
Added 16-Ball WLCSP ....................................................... Universal
Changes to Features Section............................................................ 1
Added Figure 5, Renumbered Sequentially ................................ 10
Moved Table 6 ................................................................................. 11
Changes to Figure 25 and Figure 26 ............................................. 15
Added Figure 58.............................................................................. 29
Changes to Ordering Guide .......................................................... 30
12/2010—Rev. 0 to Rev. A
Changes to Features, General Description, and Product
Highlights Sections............................................................................1
Changes to AD5629R Relative Accuracy Parameter, Reference
Output (1.25 V) Reference Input Range Parameter, and Reference
Output (2.5 V) Reference Input Range Parameter (Table 1) .......3
Changes to Relative Accuracy Parameter, Reference Tempco
Parameter (Table 2) ...........................................................................5
Changes to Output Voltage Settling Time Parameter (Table 3) ..6
Changes to Table 5.............................................................................9
Changes to CLR Pin Description (Table 6) ................................. 10
Added Figure 32 and Figure 33 .................................................... 15
Added Figure 46 ............................................................................. 17
Changes to Internal Reference Section ........................................ 20
Changes to Power-On Reset Section ........................................... 23
Changes to Clear Code Register Section ..................................... 24
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
10/2010—Revision 0: Initial Version
Rev. E | Page 2 of 32
Data Sheet
SPECIFICATIONS
AD5629R/AD5669R
V
DD
= 4.5 V to 5.5 V, R
L
= 2 kΩ to GND, C
L
= 200 pF to GND, V
REFIN
= V
DD
. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Table 1.
Parameter
STATIC PERFORMANCE
2
AD5629R
Resolution
Relative Accuracy
Differential Nonlinearity
AD5669R
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection
Ratio
DC Crosstalk
(External Reference)
A Grade
1
Min
Typ Max
B Grade
1
Min
Typ Max
Unit
Test Conditions/Comments
12
±0.5
±4
±0.25
12
±0.5
±1
±0.25
Bits
LSB
LSB
See Figure 7
Guaranteed monotonic by design
(see Figure 9)
16
±8
±32
±1
19
−1
±1
±19
16
±8
±16
±1
19
−1
±1
±19
Bits
LSB
LSB
mV
µV/°C
% FSR
% FSR
ppm
mV
dB
µV
µV/mA
µV
µV
µV/mA
6
±2
−0.2
±2.5
±6
–80
10
5
10
25
10
6
±2
−0.2
±2.5
±6
–80
10
5
10
25
10
See Figure 6
Guaranteed monotonic by design
(see Figure 8)
All 0s loaded to DAC register (see Figure 19)
All 1s loaded to DAC register (see Figure 20)
Of FSR/°C
V
DD
± 10%
Due to full-scale output change,
R
L
= 2 kΩ to GND or V
DD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
R
L
= 2 kΩ to GND or V
DD
Due to load current change
DC Crosstalk
(Internal Reference)
OUTPUT CHARACTERISTICS
Output Voltage Range
Capacitive Load Stability
3
0
2
10
0.5
30
4
40
0
14.6
1.247
±15
7.5
2.495
±15
7.5
V
DD
0
2
10
0.5
30
4
V
DD
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT (1.25 V)
Output Voltage
Reference Input Range
Output Impedance
REFERENCE OUTPUT (2.5 V)
Output Voltage
Reference Input Range
Output Impedance
V
nF
nF
Ω
mA
µs
µA
V
kΩ
µA
ppm/°C
kΩ
R
L
= ∞
R
L
= 2 kΩ
V
DD
= 5 V
Coming out of power-down mode, V
DD
= 5 V
V
REFIN
= V
DD
= 5.5 V (per DAC channel)
50
V
DD
40
0
14.6
50
V
DD
1.253
1.247
±5
±15
7.5
1.253
±15
T
A
= 25°C
LFCSP, TSSOP
WLCSP
2.505
2.495
±5
7.5
2.505
±10
µA
ppm/°C
kΩ
T
A
= 25°C
Rev. E | Page 3 of 32
AD5629R/AD5669R
Parameter
LOGIC INPUTS
3
Input Current
Input Low Voltage, V
INL
Input High Voltage, V
INH
Pin Capacitance
POWER REQUIREMENTS
V
DD
I
DD
(Normal Mode)
4
V
DD
= 4.5 V to 5.5 V
I
DD
(All Power-Down Modes)
5
V
DD
= 4.5 V to 5.5 V
1
2
Data Sheet
A Grade
1
Min
Typ Max
±3
0.8
2
3
4.5
5.5
4.5
2
3
5.5
B Grade
1
Min
Typ Max
±3
0.8
Unit
µA
V
V
pF
V
Test Conditions/Comments
All digital inputs
V
DD
= 5 V
V
DD
= 5 V
1.3
2
0.4
1.8
2.5
1
1.3
2
0.4
1.8
2.5
1
mA
mA
µA
All digital inputs at 0 or V
DD
,
DAC active, excludes load current
V
IH
= V
DD
and V
IL
= GND
Internal reference off
Internal reference on
V
IH
= V
DD
and V
IL
= GND
Temperature range is −40°C to +105°C, typical at 25°C.
Linearity calculated using a reduced code range of the
AD5629R
(Code 32 to Code 4064) and the
AD5669R
(Code 512 to 65,024). Output unloaded.
3
Guaranteed by design and characterization; not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All eight DACs powered down.
Rev. E | Page 4 of 32
Data Sheet
Table 2.
Parameter
STATIC PERFORMANCE
2
AD5629R
Resolution
Relative Accuracy
Differential Nonlinearity
AD5669R
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Zero-Code Error Drift
Full-Scale Error
Gain Error
Gain Temperature Coefficient
Offset Error
DC Power Supply Rejection
Ratio
DC Crosstalk
(External Reference)
A Grade
1
Min
Typ Max
B Grade
1
Min
Typ Max
Unit
AD5629R/AD5669R
V
DD
= 2.7 V to 3.6 V, R
L
= 2 kΩ to GND, C
L
= 200 pF to GND, V
REFIN
= V
DD
. All specifications T
MIN
to T
MAX
, unless otherwise noted.
Conditions/Comments
12
±0.5
±4
±0.25
12
±0.5
±1
±0.25
Bits
LSB
LSB
Bits
LSB
LSB
mV
µV/°C
% FSR
% FSR
ppm
mV
dB
µV
µV/mA
µV
µV
µV/mA
See Figure 7
Guaranteed monotonic by design (see Figure 9)
16
±8
6
±2
−0.2
±2.5
±6
–80
10
5
10
25
10
±32
±1
19
−1
±1
±19
16
±8
6
±2
−0.2
±2.5
±6
–80
10
5
10
25
10
V
DD
2
10
0.5
30
4
40
50
V
DD
0
2
10
0.5
30
4
40
0
14.6
50
V
DD
V
DD
±16
±1
19
−1
±1
±19
See Figure 6
Guaranteed monotonic by design (see Figure 8)
All 0s loaded to DAC register (see Figure 19)
All 1s loaded to DAC register (see Figure 20)
Of FSR/°C
V
DD
± 10%
Due to full-scale output change,
R
L
= 2 kΩ to GND or V
DD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
R
L
= 2 kΩ to GND or V
DD
Due to load current change
DC Crosstalk
(Internal Reference)
OUTPUT CHARACTERISTICS
3
Output Voltage Range
Capacitive Load Stability
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
Output Voltage
AD5629R/AD5669R
Reference Tempco
3
Reference Output Impedance
LOGIC INPUTS
3
Input Current
Input Low Voltage, V
INL
Input High Voltage, V
INH
Pin Capacitance
0
V
nF
nF
Ω
mA
µs
µA
kΩ
R
L
= ∞
R
L
= 2 kΩ
V
DD
= 3 V
Coming out of power-down mode, V
DD
= 3 V
V
REFIN
= V
DD
= 3.6 V (per DAC channel)
0
14.6
1.247
±15
7.5
1.253
1.247
±5
±15
7.5
1.253
±15
V
ppm/°C
kΩ
T
A
= 25°C
LFCSP, TSSOP
WLCSP
±3
0.8
2
3
2
3
±3
0.8
µA
V
V
pF
All digital inputs
V
DD
= 3 V
V
DD
= 3 V
Rev. E | Page 5 of 32
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